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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-04 11:29:42 +02:00
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9ed4c9d710e8ffc9bc33ecfe8f5650fc45cf5bc2
yosys/backends
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Clifford Wolf 9ed4c9d710 Improve write_aiger handling of unconnected nets and constants
2017-05-28 11:31:35 +02:00
..
aiger
Improve write_aiger handling of unconnected nets and constants
2017-05-28 11:31:35 +02:00
blif
Add $_ANDNOT_ and $_ORNOT_ gates
2017-05-17 09:08:29 +02:00
btor
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00
edif
Add generation of logic cells to EDIF back-end runtest.py
2017-03-19 14:57:40 +01:00
firrtl
More progress on Firrtl backend.
2017-02-13 11:17:53 -08:00
ilang
Added avail params to ilang format, check module params in 'hierarchy -check'
2016-10-22 11:05:49 +02:00
intersynth
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00
json
Improved write_json help message
2016-12-29 12:13:29 +01:00
simplec
Add workaround for CBMC bug to SimpleC back-end
2017-05-17 21:07:54 +02:00
smt2
Change default smt2 solver to yices (Yices 2 has switched its license to GPL)
2017-05-27 11:56:01 +02:00
smv
Add $_ANDNOT_ and $_ORNOT_ gates
2017-05-17 09:08:29 +02:00
spice
Also escape "=" in spice output
2016-05-20 16:43:13 +02:00
verilog
Add $_ANDNOT_ and $_ORNOT_ gates
2017-05-17 09:08:29 +02:00
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