mirror of https://github.com/YosysHQ/yosys.git
80 lines
1.2 KiB
Plaintext
80 lines
1.2 KiB
Plaintext
read_verilog <<EOT
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module alu_sub_3op(
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input [7:0] a, b, c,
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output [7:0] y
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);
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assign y = a - b + c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt_clean
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csa_tree
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opt_clean
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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select -assert-none t:$alu
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select -assert-none t:$sub
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design -reset
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read_verilog <<EOT
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module alu_sub_mixed(
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input [7:0] a, b, c, d,
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output [7:0] y
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);
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assign y = a + b - c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt_clean
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csa_tree
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opt_clean
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select -assert-count 3 t:$fa
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select -assert-count 1 t:$add
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select -assert-none t:$alu
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select -assert-none t:$sub
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design -reset
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read_verilog <<EOT
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module alu_sub_all(
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input [7:0] a, b, c, d,
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output [7:0] y
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);
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assign y = a - b - c - d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt_clean
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csa_tree
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opt_clean
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select -assert-count 3 t:$fa
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select -assert-count 1 t:$add
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select -assert-none t:$alu
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select -assert-none t:$sub
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design -reset
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read_verilog <<EOT
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module alu_sub_signed(
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input signed [7:0] a, b, c, d,
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output signed [9:0] y
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);
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assign y = a + b - c - d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt_clean
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csa_tree
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opt_clean
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select -assert-count 3 t:$fa
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select -assert-count 1 t:$add
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select -assert-none t:$alu
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select -assert-none t:$sub
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design -reset
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