mirror of https://github.com/YosysHQ/yosys.git
552 lines
17 KiB
C++
552 lines
17 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2024 Silimate Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/ff.h"
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#include "kernel/satgen.h"
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#include <queue>
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#include <algorithm>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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// Configuration
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static const int DEFAULT_MAX_COVER = 100; // Max candidate signals to consider
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static const int DEFAULT_MIN_NET_SIZE = 10; // Min registers per clock gate
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struct InferCeWorker
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{
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Module *module;
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SigMap sigmap;
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// Configuration
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int max_cover;
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int min_net_size;
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// Maps output signal bits to their driver cells
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dict<SigBit, Cell*> sig_to_driver;
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// Maps cell input pins to their source signals
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dict<SigBit, pool<Cell*>> sig_to_sinks;
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// Pre-computed list of combinational cells (for SAT import)
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std::vector<Cell*> comb_cells;
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// Statistics
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int accepted_count = 0;
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int rejected_sat_count = 0;
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int sat_solves = 0;
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InferCeWorker(Module *module, int max_cover, int min_net_size)
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: module(module), sigmap(module),
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max_cover(max_cover), min_net_size(min_net_size)
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{
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// Build driver and sink maps
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for (auto cell : module->cells()) {
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for (auto &conn : cell->connections()) {
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if (cell->output(conn.first)) {
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for (auto bit : sigmap(conn.second))
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if (bit.wire)
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sig_to_driver[bit] = cell;
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}
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if (cell->input(conn.first)) {
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for (auto bit : sigmap(conn.second))
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if (bit.wire)
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sig_to_sinks[bit].insert(cell);
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}
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}
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// Collect combinational cells for SAT
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if (!cell->type.in(ID($ff), ID($dff), ID($dffe), ID($adff), ID($adffe),
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ID($sdff), ID($sdffe), ID($sdffce), ID($dffsr),
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ID($dffsre), ID($_DFF_P_), ID($_DFF_N_), ID($_DFFE_PP_),
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ID($_DFFE_PN_), ID($_DFFE_NP_), ID($_DFFE_NN_))) {
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comb_cells.push_back(cell);
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}
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}
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}
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// Get upstream signals feeding into given signals (BFS backward)
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pool<SigBit> getUpstreamSignals(const pool<SigBit> &start_signals, int limit)
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{
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pool<SigBit> visited;
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std::queue<SigBit> worklist;
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for (auto bit : start_signals) {
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worklist.push(bit);
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visited.insert(bit);
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}
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while (!worklist.empty() && (int)visited.size() < limit) {
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SigBit bit = worklist.front();
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worklist.pop();
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if (!sig_to_driver.count(bit))
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continue;
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Cell *driver = sig_to_driver[bit];
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if (driver->type.in(ID($ff), ID($dff), ID($dffe), ID($adff), ID($adffe),
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ID($sdff), ID($sdffe), ID($sdffce), ID($dffsr),
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ID($dffsre), ID($_DFF_P_), ID($_DFF_N_), ID($_DFFE_PP_),
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ID($_DFFE_PN_), ID($_DFFE_NP_), ID($_DFFE_NN_)))
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continue;
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for (auto &conn : driver->connections())
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if (driver->input(conn.first))
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for (auto in_bit : sigmap(conn.second))
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if (in_bit.wire && !visited.count(in_bit)) {
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visited.insert(in_bit);
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worklist.push(in_bit);
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}
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}
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return visited;
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}
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// Get cells in the transitive fanin cone of given signals (for SAT import)
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// This is much faster than importing ALL cells
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pool<Cell*> getConeOfLogic(SigSpec sig)
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{
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pool<Cell*> cone_cells;
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pool<SigBit> visited;
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std::queue<SigBit> worklist;
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// Start from all bits in sig
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for (auto bit : sigmap(sig)) {
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if (bit.wire && !visited.count(bit)) {
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visited.insert(bit);
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worklist.push(bit);
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}
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}
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// BFS backward through drivers
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while (!worklist.empty()) {
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SigBit bit = worklist.front();
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worklist.pop();
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if (!sig_to_driver.count(bit))
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continue;
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Cell *driver = sig_to_driver[bit];
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// Skip registers
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if (driver->type.in(ID($ff), ID($dff), ID($dffe), ID($adff), ID($adffe),
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ID($sdff), ID($sdffe), ID($sdffce), ID($dffsr),
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ID($dffsre), ID($_DFF_P_), ID($_DFF_N_), ID($_DFFE_PP_),
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ID($_DFFE_PN_), ID($_DFFE_NP_), ID($_DFFE_NN_)))
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continue;
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// Add this cell to cone
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if (cone_cells.count(driver))
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continue; // Already processed
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cone_cells.insert(driver);
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// Add inputs of driver to worklist
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for (auto &conn : driver->connections()) {
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if (driver->input(conn.first)) {
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for (auto in_bit : sigmap(conn.second)) {
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if (in_bit.wire && !visited.count(in_bit)) {
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visited.insert(in_bit);
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worklist.push(in_bit);
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}
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}
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}
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}
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}
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return cone_cells;
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}
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// Check if OR/AND of signals forms a valid gating condition using SAT
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// Uses a PRE-CREATED SAT solver (passed in) to avoid recreating for each check
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bool isValidGatingSetWithSolver(ezSatPtr &ez, SatGen &satgen,
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const std::vector<SigBit> &conds,
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SigSpec sig_d, SigSpec sig_q, bool as_enable)
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{
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if (conds.empty())
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return false;
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sat_solves++;
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std::vector<int> d_vec = satgen.importSigSpec(sig_d);
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std::vector<int> q_vec = satgen.importSigSpec(sig_q);
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// Build OR (for enable) or AND (for disable) of condition signals
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std::vector<int> cond_vars;
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for (auto bit : conds)
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cond_vars.push_back(satgen.importSigSpec(SigSpec(bit))[0]);
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int combined_cond;
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if (as_enable) {
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// Clock enable: OR of signals (any signal high = enable)
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combined_cond = ez->expression(ezSAT::OpOr, cond_vars);
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} else {
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// Clock disable: AND of signals (all signals high = disable)
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combined_cond = ez->expression(ezSAT::OpAnd, cond_vars);
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}
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int d_ne_q = ez->vec_ne(d_vec, q_vec);
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// Safe gating: when gating is active (enable=0 or disable=1), D must equal Q
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int gating_active = as_enable ? ez->NOT(combined_cond) : combined_cond;
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int query = ez->AND(gating_active, d_ne_q);
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std::vector<int> assumptions = {query};
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std::vector<int> dummy_exprs;
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std::vector<bool> dummy_vals;
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bool is_valid = !ez->solve(dummy_exprs, dummy_vals, assumptions);
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if (!is_valid)
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rejected_sat_count++;
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return is_valid;
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}
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// Wrapper that creates a fresh SAT solver (used for standalone checks)
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bool isValidGatingSet(const std::vector<SigBit> &conds, SigSpec sig_d, SigSpec sig_q, bool as_enable)
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{
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if (conds.empty())
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return false;
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pool<Cell*> cone = getConeOfLogic(sig_d);
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ezSatPtr ez;
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SatGen satgen(ez.get(), &sigmap);
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for (auto cell : cone)
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satgen.importCell(cell);
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return isValidGatingSetWithSolver(ez, satgen, conds, sig_d, sig_q, as_enable);
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}
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// Binary search to minimize the gating condition set
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// Tries to remove half of the signals at a time
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// Uses pre-created SAT solver to avoid recreating for each check
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void minimizeGatingConditionWithSolver(
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ezSatPtr &ez, SatGen &satgen,
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std::vector<SigBit> &good_conds,
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std::vector<SigBit>::iterator begin,
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std::vector<SigBit>::iterator end,
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SigSpec sig_d, SigSpec sig_q, bool as_enable)
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{
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int half_len = (end - begin) / 2;
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if (half_len == 0)
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return;
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auto mid = begin + half_len;
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// Try removing [mid, end) from the condition
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std::vector<SigBit> test_conds;
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test_conds.insert(test_conds.end(), good_conds.begin(), begin);
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test_conds.insert(test_conds.end(), begin, mid);
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test_conds.insert(test_conds.end(), end, good_conds.end());
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if (!test_conds.empty() && isValidGatingSetWithSolver(ez, satgen, test_conds, sig_d, sig_q, as_enable)) {
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// Can remove [mid, end)
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good_conds.erase(mid, end);
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// Recurse on remaining half
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minimizeGatingConditionWithSolver(ez, satgen, good_conds, begin, begin + half_len, sig_d, sig_q, as_enable);
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} else {
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// Cannot remove all of [mid, end), try to minimize each half
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if (end - mid > 1)
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minimizeGatingConditionWithSolver(ez, satgen, good_conds, mid, end, sig_d, sig_q, as_enable);
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minimizeGatingConditionWithSolver(ez, satgen, good_conds, begin, mid, sig_d, sig_q, as_enable);
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}
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}
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// Wrapper for standalone use (creates fresh solver)
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void minimizeGatingCondition(
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std::vector<SigBit> &good_conds,
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std::vector<SigBit>::iterator begin,
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std::vector<SigBit>::iterator end,
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SigSpec sig_d, SigSpec sig_q, bool as_enable)
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{
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pool<Cell*> cone = getConeOfLogic(sig_d);
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ezSatPtr ez;
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SatGen satgen(ez.get(), &sigmap);
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for (auto cell : cone)
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satgen.importCell(cell);
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minimizeGatingConditionWithSolver(ez, satgen, good_conds, begin, end, sig_d, sig_q, as_enable);
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}
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// Find gating condition for a register
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// Returns: {gating_conds, is_enable, cone_size}
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std::tuple<std::vector<SigBit>, bool, int> findGatingCondition(Cell *reg)
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{
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FfData ff(nullptr, reg);
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pool<SigBit> d_inputs;
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for (auto bit : sigmap(ff.sig_d))
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if (bit.wire)
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d_inputs.insert(bit);
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pool<SigBit> upstream = getUpstreamSignals(d_inputs, max_cover);
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std::vector<SigBit> candidates;
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for (auto bit : upstream)
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candidates.push_back(bit);
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if ((int)candidates.size() > max_cover)
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candidates.resize(max_cover);
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if (candidates.empty())
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return {{}, false, 0};
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// Create SAT solver ONCE for this register
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pool<Cell*> cone = getConeOfLogic(ff.sig_d);
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int cone_size = (int)cone.size();
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// Skip registers with trivial cones (not worth gating) or huge cones (too expensive)
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const int MIN_CONE_SIZE = 2;
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const int MAX_CONE_SIZE = 500;
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if (cone_size < MIN_CONE_SIZE || cone_size > MAX_CONE_SIZE)
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return {{}, false, cone_size};
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ezSatPtr ez;
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SatGen satgen(ez.get(), &sigmap);
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for (auto cell : cone)
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satgen.importCell(cell);
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// Try as clock enable first
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if (isValidGatingSetWithSolver(ez, satgen, candidates, ff.sig_d, ff.sig_q, true)) {
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minimizeGatingConditionWithSolver(ez, satgen, candidates, candidates.begin(), candidates.end(),
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ff.sig_d, ff.sig_q, true);
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if (!candidates.empty())
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return {candidates, true, cone_size};
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}
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// Try as clock disable
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if (isValidGatingSetWithSolver(ez, satgen, candidates, ff.sig_d, ff.sig_q, false)) {
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minimizeGatingConditionWithSolver(ez, satgen, candidates, candidates.begin(), candidates.end(),
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ff.sig_d, ff.sig_q, false);
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if (!candidates.empty())
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return {candidates, false, cone_size};
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}
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return {{}, false, cone_size};
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}
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// Insert clock gating logic for a group of registers
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void insertClockGate(const std::vector<Cell*> ®s,
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const std::vector<SigBit> &gating_conds,
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bool as_enable)
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{
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if (regs.empty() || gating_conds.empty())
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return;
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// Build gating condition: OR for enable, AND for disable
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SigBit gating_signal;
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if (gating_conds.size() == 1) {
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gating_signal = gating_conds[0];
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} else {
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SigSpec cond_inputs;
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for (auto bit : gating_conds)
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cond_inputs.append(bit);
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Wire *cond_wire = module->addWire(NEW_ID);
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if (as_enable)
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module->addReduceOr(NEW_ID, cond_inputs, cond_wire);
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else
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module->addReduceAnd(NEW_ID, cond_inputs, cond_wire);
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gating_signal = cond_wire;
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}
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// If disable signal, invert to get enable
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if (!as_enable) {
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Wire *inv_wire = module->addWire(NEW_ID);
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module->addNot(NEW_ID, gating_signal, inv_wire);
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gating_signal = inv_wire;
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}
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// Add CE to each register
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for (auto reg : regs) {
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FfData ff(nullptr, reg);
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if (ff.has_ce) {
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Wire *combined_ce = module->addWire(NEW_ID);
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module->addAnd(NEW_ID, ff.sig_ce, gating_signal, combined_ce);
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ff.sig_ce = combined_ce;
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} else {
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ff.has_ce = true;
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ff.sig_ce = gating_signal;
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ff.pol_ce = true;
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}
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ff.emit();
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}
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}
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// Check if register can be added to an existing gate
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bool canReuseGate(const std::vector<SigBit> &existing_conds, Cell *reg, bool is_enable)
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{
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FfData ff(nullptr, reg);
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return isValidGatingSet(existing_conds, ff.sig_d, ff.sig_q, is_enable);
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}
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// Main processing function
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void run()
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{
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std::vector<Cell*> registers;
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for (auto cell : module->cells()) {
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if (!cell->type.in(ID($ff), ID($dff), ID($dffe), ID($adff), ID($adffe),
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ID($sdff), ID($sdffe), ID($sdffce), ID($dffsr),
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ID($dffsre), ID($_DFF_P_), ID($_DFF_N_), ID($_DFFE_PP_),
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ID($_DFFE_PN_), ID($_DFFE_NP_), ID($_DFFE_NN_)))
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continue;
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FfData ff(nullptr, cell);
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if (ff.has_ce || !ff.has_clk)
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continue;
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registers.push_back(cell);
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}
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log("Processing module %s: %zu cells, %zu flip-flops, %zu wires\n",
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log_id(module), module->cells().size(), registers.size(), module->wires().size());
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if (registers.empty())
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return;
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struct AcceptedGate {
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std::vector<SigBit> conds;
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pool<SigBit> cond_set;
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std::vector<Cell*> regs;
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bool is_enable;
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};
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std::vector<AcceptedGate> accepted_gates;
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dict<SigBit, std::vector<size_t>> net_to_accepted;
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int reg_idx = 0;
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for (auto reg : registers) {
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auto [gating_conds, is_enable, cone_size] = findGatingCondition(reg);
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log("Processing register %d/%zu: %s (cone=%d)\n", ++reg_idx, registers.size(), log_id(reg), cone_size);
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if (gating_conds.empty())
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continue;
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pool<SigBit> cond_set;
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for (auto bit : gating_conds)
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cond_set.insert(bit);
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// Find candidate gates sharing any net
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pool<size_t> candidate_gates;
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for (auto bit : gating_conds)
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if (net_to_accepted.count(bit))
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for (auto idx : net_to_accepted[bit])
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candidate_gates.insert(idx);
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// HEURISTIC: Only check limited gates for reuse
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const int MAX_REUSE_CHECKS = 20;
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bool found_match = false;
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int checked = 0;
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for (auto idx : candidate_gates) {
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if (checked >= MAX_REUSE_CHECKS)
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break;
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auto &gate = accepted_gates[idx];
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if (gate.is_enable != is_enable)
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continue;
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checked++;
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if (canReuseGate(gate.conds, reg, is_enable)) {
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gate.regs.push_back(reg);
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found_match = true;
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break;
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}
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}
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if (!found_match) {
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size_t new_idx = accepted_gates.size();
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accepted_gates.push_back({gating_conds, cond_set, {reg}, is_enable});
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for (auto bit : gating_conds)
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net_to_accepted[bit].push_back(new_idx);
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}
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}
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// Insert clock gates for groups meeting threshold
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for (auto &gate : accepted_gates) {
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if ((int)gate.regs.size() >= min_net_size) {
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insertClockGate(gate.regs, gate.conds, gate.is_enable);
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accepted_count += gate.regs.size();
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}
|
|
}
|
|
}
|
|
};
|
|
|
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struct InferCePass : public Pass {
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InferCePass() : Pass("infer_ce", "Infer clock enable signals from conditional logic") { }
|
|
|
|
void help() override
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|
{
|
|
log("\n");
|
|
log(" infer_ce [options] [selection]\n");
|
|
log("\n");
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|
log("This command infers clock enable (CE) signals from conditional logic.\n");
|
|
log("It analyzes registers and uses SAT solving to find signals that can\n");
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|
log("serve as clock enable conditions (when the signal is low, D==Q).\n");
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|
log("\n");
|
|
log("Algorithm based on:\n");
|
|
log(" - \"Automatic Synthesis of Clock Gating Logic\" by Aaron P. Hurst\n");
|
|
log(" - OpenROAD's cgt module implementation\n");
|
|
log("\n");
|
|
log(" -max_cover <n>\n");
|
|
log(" maximum number of candidate signals to consider per register\n");
|
|
log(" (default: %d)\n", DEFAULT_MAX_COVER);
|
|
log("\n");
|
|
log(" -min_net_size <n>\n");
|
|
log(" minimum number of registers that must share a gating condition\n");
|
|
log(" for a clock gate to be inserted (default: %d)\n", DEFAULT_MIN_NET_SIZE);
|
|
log("\n");
|
|
}
|
|
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
|
{
|
|
log_header(design, "Executing INFER_CE pass.\n");
|
|
|
|
int max_cover = DEFAULT_MAX_COVER;
|
|
int min_net_size = DEFAULT_MIN_NET_SIZE;
|
|
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++) {
|
|
if (args[argidx] == "-max_cover" && argidx+1 < args.size()) {
|
|
max_cover = std::stoi(args[++argidx]);
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-min_net_size" && argidx+1 < args.size()) {
|
|
min_net_size = std::stoi(args[++argidx]);
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
extra_args(args, argidx, design);
|
|
|
|
int total_gates = 0;
|
|
for (auto module : design->selected_modules()) {
|
|
InferCeWorker worker(module, max_cover, min_net_size);
|
|
worker.run();
|
|
total_gates += worker.accepted_count;
|
|
}
|
|
|
|
log("Inserted clock enables for %d registers.\n", total_gates);
|
|
}
|
|
} InferCePass;
|
|
|
|
PRIVATE_NAMESPACE_END
|