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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-06 20:12:09 +02:00
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9bb839c613aff1d7658eac8ec46c3dcd3b220c5f
yosys/techlibs/common
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Marcelina Kościelnicka cde73428b0 Fix syntax error in adff2dff.v
Fixes #2600.
2021-02-24 01:07:34 +01:00
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.gitignore
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abc9_map.v
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abc9_model.v
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abc9_unmap.v
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adff2dff.v
Fix syntax error in adff2dff.v
2021-02-24 01:07:34 +01:00
cellhelp.py
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cells.lib
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cmp2lcu.v
verilog: significant block scoping improvements
2021-01-31 09:42:09 -05:00
cmp2lut.v
verilog: significant block scoping improvements
2021-01-31 09:42:09 -05:00
dff2ff.v
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gate2lut.v
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gen_fine_ffs.py
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Makefile.inc
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mul2dsp.v
verilog: significant block scoping improvements
2021-01-31 09:42:09 -05:00
pmux2mux.v
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prep.cc
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simcells.v
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simlib.v
Fix some trivial typos.
2021-01-03 23:52:59 -08:00
synth.cc
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techmap.v
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