yosys/tests/verific
Akash Levy 3e9a5c68b1 Switch back to main Verific without VHDL support 2026-02-18 21:57:14 -08:00
..
README.md Switch back to main Verific without VHDL support 2026-02-18 21:57:14 -08:00
blackbox.ys.DISABLED Revert back to using Verific naming 2025-02-13 19:40:33 -08:00
blackbox_empty.ys.DISABLED Revert back to using Verific naming 2025-02-13 19:40:33 -08:00
blackbox_ql.ys.DISABLED Revert back to using Verific naming 2025-02-13 19:40:33 -08:00
bounds.sv bound attributes: handle vhdl null ranges 2024-12-12 11:42:39 +01:00
bounds.vhd bound attributes: handle vhdl null ranges 2024-12-12 11:42:39 +01:00
case.sv Add test example 2023-02-27 09:24:04 +01:00
case.ys Revert back to using Verific naming 2025-02-13 19:40:33 -08:00
chformal.ys.DISABLED Remove chformal test from verific since it requires initial value preservation 2025-07-21 18:07:49 -07:00
clocking.ys Revert clocking.ys 2025-02-13 20:32:17 -08:00
enum_values.sv verific: Fix enum_values support and signed attribute values 2023-03-15 09:51:36 +01:00
enum_values.ys verific: Fix enum_values support and signed attribute values 2023-03-15 09:51:36 +01:00
ext_ramnet_err.sv add tests 2025-10-14 15:48:16 +02:00
ext_ramnet_err.ys Fix broken Yosys test 2025-10-26 11:40:13 -07:00
import_warning_operator.vhd add tests 2025-10-14 15:48:16 +02:00
memory_semantics.ys.DISABLED Revert back to using Verific naming 2025-02-13 19:40:33 -08:00
mixed_flist.flist tests/verific: add mixed -f list case 2026-01-28 03:55:42 -08:00
mixed_flist.sv tests/verific: ensure mixed -f requires VHDL unit 2026-01-28 22:46:10 -08:00
mixed_flist.vhd tests/verific: add mixed -f list case 2026-01-28 03:55:42 -08:00
mixed_flist.ys.DISABLED Switch back to main Verific without VHDL support 2026-02-18 21:57:14 -08:00
port_bus_order.ys Set `port_id` for Verific PortBus wires 2025-10-23 20:51:53 +00:00
range_case.sv Added ranged case check 2023-02-27 09:24:04 +01:00
range_case.ys Revert back to using Verific naming 2025-02-13 19:40:33 -08:00
rom_case.ys.DISABLED Revert back to using Verific naming 2025-02-13 19:40:33 -08:00
run-test.sh Update run-test.sh 2025-12-16 04:16:03 -08:00
setenv.flist add setenv pass 2024-12-06 11:25:43 +01:00
setenv.ys Revert back to using Verific naming 2025-02-13 19:40:33 -08:00
sva_continue_on_err.ys verific: New `-sva-continue-on-error` import option 2025-09-24 18:58:54 +02:00
sva_continue_on_err_explosion.ys verific: Extend -sva-continue-on-err to handle FSM explosion 2025-09-27 21:13:02 +02:00
sva_no_continue_on_err.ys verific: New `-sva-continue-on-error` import option 2025-09-24 18:58:54 +02:00

README.md

Verific Test Cases

Disabled

  • import_warning_operator: no VHDL
  • mixed_flist: no VHDL
  • memory_semantics: relies on initial values being retained, which we do not want
  • rom_case: we need different behavior for multi-port memories
  • blackbox*: we need different behavior for parametrized blackboxes
  • chformal: relies on initial values being retained, which we do not want