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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 18:13:40 +02:00
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99aff5a0f9f322bf4498fe06094de9919ed56681
yosys/frontends/verilog
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Eddie Hung eb5eb60fd4 verilog: fix specify src attribute
2020-05-04 10:53:06 -07:00
..
.gitignore
Add "make coverage"
2018-08-27 14:22:21 +02:00
const2ast.cc
Replacing log_error for log_file_error due consistency
2020-03-31 12:01:29 -06:00
Makefile.inc
Add one mode dependency
2020-03-19 16:53:40 +01:00
preproc.cc
Add support for SystemVerilog-style `define to Verilog frontend
2020-03-27 16:08:26 +00:00
preproc.h
Add support for SystemVerilog-style `define to Verilog frontend
2020-03-27 16:08:26 +00:00
verilog_frontend.cc
Merge pull request #1811 from PeterCrozier/typedef_scope
2020-03-30 13:55:39 +02:00
verilog_frontend.h
Merge pull request #1811 from PeterCrozier/typedef_scope
2020-03-30 13:55:39 +02:00
verilog_lexer.l
Error duplicate declarations of a typedef name in the same scope.
2020-03-24 14:35:21 +00:00
verilog_parser.y
verilog: fix specify src attribute
2020-05-04 10:53:06 -07:00
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