mirror of https://github.com/YosysHQ/yosys.git
31 lines
475 B
Systemverilog
31 lines
475 B
Systemverilog
module test_case (
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input wire clk,
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input wire rst_n,
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input wire in_val,
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output wire out_a,
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output wire out_b,
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output wire out_c,
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output wire out_d
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);
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reg a, b, c, d;
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always @(posedge clk) begin
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if (!rst_n) begin
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a <= 1'b0;
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b <= 1'b0;
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c <= 1'b0;
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d <= 1'b0;
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end else begin
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a <= c & in_val;
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b <= d & in_val;
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c <= b | in_val;
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d <= a | in_val;
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end
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end
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assign out_a = a;
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assign out_b = b;
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assign out_c = c;
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assign out_d = d;
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endmodule
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