mirror of https://github.com/YosysHQ/yosys.git
232 lines
9.2 KiB
Systemverilog
232 lines
9.2 KiB
Systemverilog
module test_case (
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input wire clk,
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input wire rst_n,
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input wire [3:0] chan_0_data,
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input wire chan_0_vld,
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input wire chan_1_rdy,
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output wire chan_0_rdy,
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output wire [207:0] chan_1_data,
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output wire chan_1_vld,
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output wire idle
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);
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wire [12:0] state_init[0:15];
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assign state_init[0] = 13'h0000;
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assign state_init[1] = 13'h0000;
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assign state_init[2] = 13'h0000;
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assign state_init[3] = 13'h0000;
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assign state_init[4] = 13'h0000;
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assign state_init[5] = 13'h0000;
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assign state_init[6] = 13'h0000;
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assign state_init[7] = 13'h0000;
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assign state_init[8] = 13'h0000;
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assign state_init[9] = 13'h0000;
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assign state_init[10] = 13'h0000;
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assign state_init[11] = 13'h0000;
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assign state_init[12] = 13'h0000;
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assign state_init[13] = 13'h0000;
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assign state_init[14] = 13'h0000;
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assign state_init[15] = 13'h0000;
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wire [12:0] ch1_init[0:15];
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assign ch1_init[0] = 13'h0000;
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assign ch1_init[1] = 13'h0000;
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assign ch1_init[2] = 13'h0000;
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assign ch1_init[3] = 13'h0000;
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assign ch1_init[4] = 13'h0000;
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assign ch1_init[5] = 13'h0000;
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assign ch1_init[6] = 13'h0000;
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assign ch1_init[7] = 13'h0000;
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assign ch1_init[8] = 13'h0000;
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assign ch1_init[9] = 13'h0000;
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assign ch1_init[10] = 13'h0000;
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assign ch1_init[11] = 13'h0000;
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assign ch1_init[12] = 13'h0000;
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assign ch1_init[13] = 13'h0000;
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assign ch1_init[14] = 13'h0000;
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assign ch1_init[15] = 13'h0000;
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wire [12:0] mask_1fff[0:15];
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assign mask_1fff[0] = 13'h1fff;
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assign mask_1fff[1] = 13'h1fff;
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assign mask_1fff[2] = 13'h1fff;
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assign mask_1fff[3] = 13'h1fff;
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assign mask_1fff[4] = 13'h1fff;
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assign mask_1fff[5] = 13'h1fff;
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assign mask_1fff[6] = 13'h1fff;
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assign mask_1fff[7] = 13'h1fff;
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assign mask_1fff[8] = 13'h1fff;
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assign mask_1fff[9] = 13'h1fff;
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assign mask_1fff[10] = 13'h1fff;
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assign mask_1fff[11] = 13'h1fff;
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assign mask_1fff[12] = 13'h1fff;
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assign mask_1fff[13] = 13'h1fff;
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assign mask_1fff[14] = 13'h1fff;
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assign mask_1fff[15] = 13'h1fff;
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reg [12:0] state_array[0:15];
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reg [3:0] ch0_in_buf;
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reg ch0_in_buf_vld;
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reg [12:0] ch1_out_buf[0:15];
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reg ch1_out_buf_vld;
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reg stg1_vld;
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wire ch1_not_vld;
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wire [3:0] ch0_sel_data;
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wire ch0_is_vld;
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wire ch1_vld_we;
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wire ch1_data_we;
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wire stg0_vld_out;
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wire ch0_buf_ready;
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wire ch0_pipe_stall;
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wire [1:0] sel_concat;
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wire ch0_buf_data_we;
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wire ch0_buf_vld_rst;
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wire stg0_idle;
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wire stg1_idle;
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wire ch0_is_inactive;
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wire ch1_is_inactive;
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wire [12:0] next_state_val[0:15];
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wire state_we;
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wire ch0_buf_vld_we;
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wire stg1_vld_we;
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wire pipe_idle;
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assign ch1_not_vld = ~ch1_out_buf_vld;
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assign ch0_sel_data = ch0_in_buf_vld ? ch0_in_buf : chan_0_data;
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assign ch0_is_vld = chan_0_vld | ch0_in_buf_vld;
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assign ch1_vld_we = chan_1_rdy | ch1_not_vld;
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assign ch1_data_we = ch0_is_vld & ch1_vld_we;
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assign stg0_vld_out = ch0_is_vld & ch1_data_we;
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assign ch0_buf_ready = ~ch0_in_buf_vld;
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assign ch0_pipe_stall = ~stg0_vld_out;
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assign sel_concat = {ch0_is_vld & ch0_sel_data[0], ch0_is_vld & ~ch0_sel_data[0]};
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assign ch0_buf_data_we = chan_0_vld & ch0_buf_ready & ch0_pipe_stall;
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assign ch0_buf_vld_rst = ch0_in_buf_vld & stg0_vld_out;
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assign stg0_idle = ~ch0_is_vld;
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assign stg1_idle = ~stg1_vld;
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assign ch0_is_inactive = ~(chan_0_vld & ch0_buf_ready);
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assign ch1_is_inactive = ~(ch1_out_buf_vld & chan_1_rdy);
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assign next_state_val[0] = state_array[0] & {13{sel_concat[0]}} | mask_1fff[0] & {13{sel_concat[1]}};
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assign next_state_val[1] = state_array[1] & {13{sel_concat[0]}} | mask_1fff[1] & {13{sel_concat[1]}};
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assign next_state_val[2] = state_array[2] & {13{sel_concat[0]}} | mask_1fff[2] & {13{sel_concat[1]}};
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assign next_state_val[3] = state_array[3] & {13{sel_concat[0]}} | mask_1fff[3] & {13{sel_concat[1]}};
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assign next_state_val[4] = state_array[4] & {13{sel_concat[0]}} | mask_1fff[4] & {13{sel_concat[1]}};
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assign next_state_val[5] = state_array[5] & {13{sel_concat[0]}} | mask_1fff[5] & {13{sel_concat[1]}};
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assign next_state_val[6] = state_array[6] & {13{sel_concat[0]}} | mask_1fff[6] & {13{sel_concat[1]}};
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assign next_state_val[7] = state_array[7] & {13{sel_concat[0]}} | mask_1fff[7] & {13{sel_concat[1]}};
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assign next_state_val[8] = state_array[8] & {13{sel_concat[0]}} | mask_1fff[8] & {13{sel_concat[1]}};
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assign next_state_val[9] = state_array[9] & {13{sel_concat[0]}} | mask_1fff[9] & {13{sel_concat[1]}};
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assign next_state_val[10] = state_array[10] & {13{sel_concat[0]}} | mask_1fff[10] & {13{sel_concat[1]}};
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assign next_state_val[11] = state_array[11] & {13{sel_concat[0]}} | mask_1fff[11] & {13{sel_concat[1]}};
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assign next_state_val[12] = state_array[12] & {13{sel_concat[0]}} | mask_1fff[12] & {13{sel_concat[1]}};
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assign next_state_val[13] = state_array[13] & {13{sel_concat[0]}} | mask_1fff[13] & {13{sel_concat[1]}};
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assign next_state_val[14] = state_array[14] & {13{sel_concat[0]}} | mask_1fff[14] & {13{sel_concat[1]}};
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assign next_state_val[15] = state_array[15] & {13{sel_concat[0]}} | mask_1fff[15] & {13{sel_concat[1]}};
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assign state_we = stg0_vld_out & ch0_sel_data[0] | stg0_vld_out & ~ch0_sel_data[0];
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assign ch0_buf_vld_we = ch0_buf_data_we | ch0_buf_vld_rst;
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assign stg1_vld_we = stg0_vld_out | stg1_vld;
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assign pipe_idle = stg0_idle & stg1_idle & ch0_is_inactive & ch1_is_inactive;
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always @(posedge clk) begin
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if (!rst_n) begin
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state_array[0] <= state_init[0];
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state_array[1] <= state_init[1];
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state_array[2] <= state_init[2];
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state_array[3] <= state_init[3];
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state_array[4] <= state_init[4];
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state_array[5] <= state_init[5];
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state_array[6] <= state_init[6];
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state_array[7] <= state_init[7];
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state_array[8] <= state_init[8];
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state_array[9] <= state_init[9];
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state_array[10] <= state_init[10];
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state_array[11] <= state_init[11];
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state_array[12] <= state_init[12];
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state_array[13] <= state_init[13];
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state_array[14] <= state_init[14];
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state_array[15] <= state_init[15];
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ch0_in_buf <= 4'h0;
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ch0_in_buf_vld <= 1'h0;
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ch1_out_buf[0] <= ch1_init[0];
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ch1_out_buf[1] <= ch1_init[1];
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ch1_out_buf[2] <= ch1_init[2];
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ch1_out_buf[3] <= ch1_init[3];
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ch1_out_buf[4] <= ch1_init[4];
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ch1_out_buf[5] <= ch1_init[5];
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ch1_out_buf[6] <= ch1_init[6];
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ch1_out_buf[7] <= ch1_init[7];
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ch1_out_buf[8] <= ch1_init[8];
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ch1_out_buf[9] <= ch1_init[9];
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ch1_out_buf[10] <= ch1_init[10];
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ch1_out_buf[11] <= ch1_init[11];
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ch1_out_buf[12] <= ch1_init[12];
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ch1_out_buf[13] <= ch1_init[13];
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ch1_out_buf[14] <= ch1_init[14];
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ch1_out_buf[15] <= ch1_init[15];
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ch1_out_buf_vld <= 1'h0;
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stg1_vld <= 1'h0;
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end else begin
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state_array[0] <= state_we ? next_state_val[0] : state_array[0];
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state_array[1] <= state_we ? next_state_val[1] : state_array[1];
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state_array[2] <= state_we ? next_state_val[2] : state_array[2];
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state_array[3] <= state_we ? next_state_val[3] : state_array[3];
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state_array[4] <= state_we ? next_state_val[4] : state_array[4];
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state_array[5] <= state_we ? next_state_val[5] : state_array[5];
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state_array[6] <= state_we ? next_state_val[6] : state_array[6];
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state_array[7] <= state_we ? next_state_val[7] : state_array[7];
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state_array[8] <= state_we ? next_state_val[8] : state_array[8];
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state_array[9] <= state_we ? next_state_val[9] : state_array[9];
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state_array[10] <= state_we ? next_state_val[10] : state_array[10];
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state_array[11] <= state_we ? next_state_val[11] : state_array[11];
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state_array[12] <= state_we ? next_state_val[12] : state_array[12];
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state_array[13] <= state_we ? next_state_val[13] : state_array[13];
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state_array[14] <= state_we ? next_state_val[14] : state_array[14];
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state_array[15] <= state_we ? next_state_val[15] : state_array[15];
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ch0_in_buf <= ch0_buf_data_we ? chan_0_data : ch0_in_buf;
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ch0_in_buf_vld <= ch0_buf_vld_we ? ch0_buf_ready : ch0_in_buf_vld;
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ch1_out_buf[0] <= ch1_data_we ? state_array[0] : ch1_out_buf[0];
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ch1_out_buf[1] <= ch1_data_we ? state_array[1] : ch1_out_buf[1];
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ch1_out_buf[2] <= ch1_data_we ? state_array[2] : ch1_out_buf[2];
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ch1_out_buf[3] <= ch1_data_we ? state_array[3] : ch1_out_buf[3];
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ch1_out_buf[4] <= ch1_data_we ? state_array[4] : ch1_out_buf[4];
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ch1_out_buf[5] <= ch1_data_we ? state_array[5] : ch1_out_buf[5];
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ch1_out_buf[6] <= ch1_data_we ? state_array[6] : ch1_out_buf[6];
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ch1_out_buf[7] <= ch1_data_we ? state_array[7] : ch1_out_buf[7];
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ch1_out_buf[8] <= ch1_data_we ? state_array[8] : ch1_out_buf[8];
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ch1_out_buf[9] <= ch1_data_we ? state_array[9] : ch1_out_buf[9];
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ch1_out_buf[10] <= ch1_data_we ? state_array[10] : ch1_out_buf[10];
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ch1_out_buf[11] <= ch1_data_we ? state_array[11] : ch1_out_buf[11];
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ch1_out_buf[12] <= ch1_data_we ? state_array[12] : ch1_out_buf[12];
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ch1_out_buf[13] <= ch1_data_we ? state_array[13] : ch1_out_buf[13];
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ch1_out_buf[14] <= ch1_data_we ? state_array[14] : ch1_out_buf[14];
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ch1_out_buf[15] <= ch1_data_we ? state_array[15] : ch1_out_buf[15];
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ch1_out_buf_vld <= ch1_vld_we ? ch0_is_vld : ch1_out_buf_vld;
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stg1_vld <= stg1_vld_we ? stg0_vld_out : stg1_vld;
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end
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end
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assign chan_0_rdy = ch0_buf_ready;
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assign chan_1_data = {
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ch1_out_buf[15],
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ch1_out_buf[14],
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ch1_out_buf[13],
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ch1_out_buf[12],
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ch1_out_buf[11],
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ch1_out_buf[10],
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ch1_out_buf[9],
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ch1_out_buf[8],
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ch1_out_buf[7],
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ch1_out_buf[6],
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ch1_out_buf[5],
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ch1_out_buf[4],
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ch1_out_buf[3],
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ch1_out_buf[2],
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ch1_out_buf[1],
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ch1_out_buf[0]
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};
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assign chan_1_vld = ch1_out_buf_vld;
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assign idle = pipe_idle;
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endmodule
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