mirror of https://github.com/YosysHQ/yosys.git
352 lines
11 KiB
C++
352 lines
11 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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* Copyright (C) 2018 Ruben Undheim <ruben.undheim@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys_common.h"
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#include "passes/hierarchy/util/verilog.h"
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#include "passes/hierarchy/util/positionals.h"
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PRIVATE_NAMESPACE_BEGIN
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USING_YOSYS_NAMESPACE
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// Find a matching wire for an implicit port connection; traversing generate block scope
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RTLIL::Wire *find_implicit_port_wire(Module *module, Cell *cell, const std::string& port)
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{
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const std::string &cellname = cell->name.str();
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size_t idx = cellname.size();
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while ((idx = cellname.find_last_of('.', idx-1)) != std::string::npos) {
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Wire *found = module->wire(cellname.substr(0, idx+1) + port.substr(1));
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if (found != nullptr)
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return found;
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}
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return module->wire(port);
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}
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PRIVATE_NAMESPACE_END
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YOSYS_NAMESPACE_BEGIN
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namespace Hierarchy {
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void resolve_verilog(Design* design, bool nodefaults, bool keep_positionals, bool keep_portwidths, bool top_is_from_verific) {
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if (!keep_positionals)
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resolve_positionals(design);
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// Determine default values
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dict<IdString, dict<IdString, Const>> defaults_db;
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if (!nodefaults)
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{
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for (auto module : design->modules())
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for (auto wire : module->wires())
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if (wire->port_input && wire->attributes.count(ID::defaultvalue))
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defaults_db[module->name][wire->name] = wire->attributes.at(ID::defaultvalue);
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}
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// Process SV implicit wildcard port connections
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std::set<Module*> blackbox_derivatives;
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std::vector<Module*> design_modules = design->modules();
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for (auto module : design_modules)
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for (auto cell : module->cells())
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resolve_wildcards(cell, blackbox_derivatives, nodefaults, defaults_db);
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if (!nodefaults)
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{
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for (auto module : design->modules())
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for (auto cell : module->cells())
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{
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if (defaults_db.count(cell->type) == 0)
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continue;
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if (keep_positionals) {
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bool found_positionals = false;
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for (auto &conn : cell->connections())
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if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9')
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found_positionals = true;
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if (found_positionals)
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continue;
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}
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for (auto &it : defaults_db.at(cell->type))
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if (!cell->hasPort(it.first))
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cell->setPort(it.first, it.second);
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}
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}
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for (auto module : design_modules)
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resolve_wand_wor(module, blackbox_derivatives, keep_portwidths, top_is_from_verific);
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for (auto module : blackbox_derivatives)
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design->remove(module);
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}
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void resolve_wildcards(Cell* cell, std::set<Module*>& blackbox_derivatives, bool nodefaults, dict<IdString, dict<IdString, Const>>& defaults_db) {
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if (!cell->get_bool_attribute(ID::wildcard_port_conns))
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return;
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Module* module = cell->module;
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Design* design = module->design;
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Module* submod = design->module(cell->type);
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if (submod == nullptr)
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log_error("Cell %s.%s (%s) has implicit port connections but the module it instantiates is unknown.\n",
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RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
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// Need accurate port widths for error checking; so must derive blackboxes with dynamic port widths
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if (submod->get_blackbox_attribute() && !cell->parameters.empty() && submod->get_bool_attribute(ID::dynports)) {
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IdString new_m_name = submod->derive(design, cell->parameters, true);
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if (new_m_name.empty())
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return;
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if (new_m_name != submod->name) {
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submod = design->module(new_m_name);
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blackbox_derivatives.insert(submod);
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}
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}
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auto old_connections = cell->connections();
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for (auto wire : submod->wires()) {
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// Find ports of the module that aren't explicitly connected
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if (!wire->port_input && !wire->port_output)
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continue;
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if (old_connections.count(wire->name))
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continue;
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// Make sure a wire of correct name exists in the parent
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Wire* parent_wire = find_implicit_port_wire(module, cell, wire->name.str());
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// Missing wires are OK when a default value is set
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if (!nodefaults && parent_wire == nullptr && defaults_db.count(cell->type) && defaults_db.at(cell->type).count(wire->name))
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continue;
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if (parent_wire == nullptr)
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log_error("No matching wire for implicit port connection `%s' of cell %s.%s (%s).\n",
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RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
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if (parent_wire->width != wire->width)
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log_error("Width mismatch between wire (%d bits) and port (%d bits) for implicit port connection `%s' of cell %s.%s (%s).\n",
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parent_wire->width, wire->width,
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RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
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cell->setPort(wire->name, parent_wire);
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}
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cell->attributes.erase(ID::wildcard_port_conns);
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}
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void resolve_wand_wor(Module* module, std::set<Module*>& blackbox_derivatives, bool keep_portwidths, bool top_is_from_verific) {
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Design* design = module->design;
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pool<Wire*> wand_wor_index;
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dict<Wire*, SigSpec> wand_map, wor_map;
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vector<SigSig> new_connections;
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for (auto wire : module->wires())
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{
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if (wire->get_bool_attribute(ID::wand)) {
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wand_map[wire] = SigSpec();
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wand_wor_index.insert(wire);
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}
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if (wire->get_bool_attribute(ID::wor)) {
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wor_map[wire] = SigSpec();
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wand_wor_index.insert(wire);
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}
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}
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for (auto &conn : module->connections())
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{
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SigSig new_conn;
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int cursor = 0;
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for (auto c : conn.first.chunks())
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{
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Wire *w = c.wire;
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SigSpec rhs = conn.second.extract(cursor, GetSize(c));
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if (wand_wor_index.count(w) == 0) {
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new_conn.first.append(c);
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new_conn.second.append(rhs);
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} else {
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if (wand_map.count(w)) {
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SigSpec sig = SigSpec(State::S1, GetSize(w));
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sig.replace(c.offset, rhs);
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wand_map.at(w).append(sig);
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} else {
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SigSpec sig = SigSpec(State::S0, GetSize(w));
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sig.replace(c.offset, rhs);
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wor_map.at(w).append(sig);
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}
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}
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cursor += GetSize(c);
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}
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new_connections.push_back(new_conn);
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}
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module->new_connections(new_connections);
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for (auto cell : module->cells())
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{
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if (!cell->known())
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continue;
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for (auto &conn : cell->connections())
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{
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if (!cell->output(conn.first))
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continue;
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SigSpec new_sig;
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bool update_port = false;
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for (auto c : conn.second.chunks())
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{
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Wire *w = c.wire;
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if (wand_wor_index.count(w) == 0) {
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new_sig.append(c);
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continue;
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}
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Wire *t = module->addWire(NEW_ID, GetSize(c));
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new_sig.append(t);
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update_port = true;
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if (wand_map.count(w)) {
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SigSpec sig = SigSpec(State::S1, GetSize(w));
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sig.replace(c.offset, t);
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wand_map.at(w).append(sig);
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} else {
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SigSpec sig = SigSpec(State::S0, GetSize(w));
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sig.replace(c.offset, t);
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wor_map.at(w).append(sig);
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}
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}
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if (update_port)
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cell->setPort(conn.first, new_sig);
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}
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}
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for (auto w : wand_wor_index)
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{
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bool wand = wand_map.count(w);
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SigSpec sigs = wand ? wand_map.at(w) : wor_map.at(w);
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if (GetSize(sigs) == 0)
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continue;
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if (GetSize(w) == 1) {
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if (wand)
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module->addReduceAnd(NEW_ID, sigs, w);
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else
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module->addReduceOr(NEW_ID, sigs, w);
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continue;
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}
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SigSpec s = sigs.extract(0, GetSize(w));
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for (int i = GetSize(w); i < GetSize(sigs); i += GetSize(w)) {
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if (wand)
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s = module->And(NEW_ID, s, sigs.extract(i, GetSize(w)));
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else
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s = module->Or(NEW_ID, s, sigs.extract(i, GetSize(w)));
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}
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module->connect(w, s);
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}
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for (auto cell : module->cells())
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{
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Module *m = design->module(cell->type);
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if (m == nullptr)
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continue;
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bool boxed_params = false;
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if (m->get_blackbox_attribute() && !cell->parameters.empty()) {
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if (m->get_bool_attribute(ID::dynports)) {
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IdString new_m_name = m->derive(design, cell->parameters, true);
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if (new_m_name.empty())
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continue;
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if (new_m_name != m->name) {
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m = design->module(new_m_name);
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blackbox_derivatives.insert(m);
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}
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} else {
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boxed_params = true;
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}
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}
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for (auto &conn : cell->connections())
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{
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Wire *w = m->wire(conn.first);
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if (w == nullptr || w->port_id == 0)
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continue;
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if (GetSize(conn.second) == 0)
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continue;
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SigSpec sig = conn.second;
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bool resize_widths = !keep_portwidths && GetSize(w) != GetSize(conn.second);
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if (resize_widths && top_is_from_verific && boxed_params)
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log_debug("Ignoring width mismatch on %s.%s.%s from verific, is port width parametrizable?\n",
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log_id(module), log_id(cell), log_id(conn.first)
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);
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else if (resize_widths) {
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if (GetSize(w) < GetSize(conn.second))
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{
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int n = GetSize(conn.second) - GetSize(w);
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if (!w->port_input && w->port_output)
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{
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RTLIL::SigSpec out = sig.extract(0, GetSize(w));
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out.extend_u0(GetSize(sig), w->is_signed);
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module->connect(sig.extract(GetSize(w), n), out.extract(GetSize(w), n));
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}
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sig.remove(GetSize(w), n);
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}
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else
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{
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int n = GetSize(w) - GetSize(conn.second);
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if (w->port_input && !w->port_output)
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sig.extend_u0(GetSize(w), sig.is_wire() && sig.as_wire()->is_signed);
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else
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sig.append(module->addWire(NEW_ID, n));
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}
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if (!conn.second.is_fully_const() || !w->port_input || w->port_output)
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log_warning("Resizing cell port %s.%s.%s from %d bits to %d bits.\n", log_id(module), log_id(cell),
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log_id(conn.first), GetSize(conn.second), GetSize(sig));
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cell->setPort(conn.first, sig);
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}
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if (w->port_output && !w->port_input && sig.has_const())
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log_error("Output port %s.%s.%s (%s) is connected to constants: %s\n",
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log_id(module), log_id(cell), log_id(conn.first), log_id(cell->type), log_signal(sig));
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}
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}
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}
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void check_supported_formal(Design* design) {
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for (auto mod : design->modules()) {
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for (auto cell : mod->cells()) {
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if (!cell->type.in(ID($check), ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
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continue;
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if (!cell->has_attribute(ID(unsupported_sva)))
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continue;
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auto src = cell->get_src_attribute();
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if (!src.empty())
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src += ": ";
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log_error("%sProperty `%s' in module `%s' uses unsupported SVA constructs. See frontend warnings for details, run `chformal -remove a:unsupported_sva' to ignore.\n",
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src, log_id(cell->name), log_id(mod->name));
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}
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}
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}
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};
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YOSYS_NAMESPACE_END
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