mirror of https://github.com/YosysHQ/yosys.git
94 lines
3.4 KiB
C++
94 lines
3.4 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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* Copyright (C) 2018 Ruben Undheim <ruben.undheim@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys_common.h"
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#include "passes/hierarchy/util/positionals.h"
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#include "passes/hierarchy/util/misc.h"
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YOSYS_NAMESPACE_BEGIN
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namespace Hierarchy {
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void resolve_positionals(RTLIL::Design* design) {
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std::set<RTLIL::Module*> pos_mods;
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std::map<std::pair<RTLIL::Module*,int>, RTLIL::IdString> pos_map;
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std::vector<std::pair<RTLIL::Module*,RTLIL::Cell*>> pos_work;
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for (auto mod : design->modules())
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for (auto cell : mod->cells()) {
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RTLIL::Module *cell_mod = design->module(cell->type);
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if (cell_mod == nullptr)
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continue;
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for (auto &conn : cell->connections())
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if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
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pos_mods.insert(design->module(cell->type));
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pos_work.push_back(std::pair<RTLIL::Module*,RTLIL::Cell*>(mod, cell));
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break;
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}
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pool<std::pair<IdString, IdString>> params_rename;
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for (const auto &p : cell->parameters) {
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int id;
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if (read_id_num(p.first, &id)) {
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if (id <= 0 || id > GetSize(cell_mod->avail_parameters)) {
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log(" Failed to map positional parameter %d of cell %s.%s (%s).\n",
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id, RTLIL::id2cstr(mod->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
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} else {
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params_rename.insert(std::make_pair(p.first, cell_mod->avail_parameters[id - 1]));
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}
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}
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}
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for (const auto &p : params_rename) {
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cell->setParam(p.second, cell->getParam(p.first));
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cell->unsetParam(p.first);
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}
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}
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for (auto module : pos_mods)
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for (auto wire : module->wires()) {
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if (wire->port_id > 0)
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pos_map[std::pair<RTLIL::Module*,int>(module, wire->port_id)] = wire->name;
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}
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for (auto &work : pos_work) {
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RTLIL::Module *module = work.first;
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RTLIL::Cell *cell = work.second;
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log("Mapping positional arguments of cell %s.%s (%s).\n",
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RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
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dict<RTLIL::IdString, RTLIL::SigSpec> new_connections;
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for (auto &conn : cell->connections()) {
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int id;
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if (read_id_num(conn.first, &id)) {
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std::pair<RTLIL::Module*,int> key(design->module(cell->type), id);
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if (pos_map.count(key) == 0) {
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log(" Failed to map positional argument %d of cell %s.%s (%s).\n",
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id, RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
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new_connections[conn.first] = conn.second;
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} else
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new_connections[pos_map.at(key)] = conn.second;
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} else
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new_connections[conn.first] = conn.second;
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}
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cell->connections_ = new_connections;
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}
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}
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};
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YOSYS_NAMESPACE_END
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