mirror of https://github.com/YosysHQ/yosys.git
80 lines
3.2 KiB
C++
80 lines
3.2 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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* Copyright (C) 2018 Ruben Undheim <ruben.undheim@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef HIERARCHY_INTERFACES_H
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#define HIERARCHY_INTERFACES_H
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#include "kernel/yosys.h"
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YOSYS_NAMESPACE_BEGIN
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namespace Hierarchy {
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void expand_all_interfaces(Design* design, Module* top_mod, bool flag_check, bool flag_simcheck, bool flag_smtcheck, const std::vector<std::string> &libdirs);
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bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check, bool flag_simcheck, bool flag_smtcheck, const std::vector<std::string> &libdirs);
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// For expanding a module's interface connections
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struct IFExpander
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{
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IFExpander (RTLIL::Design &design, RTLIL::Module &m);
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RTLIL::Module &module;
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dict<RTLIL::IdString, RTLIL::Module*> interfaces_in_module;
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bool has_interfaces_not_found;
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std::vector<RTLIL::IdString> connections_to_remove;
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std::vector<RTLIL::IdString> connections_to_add_name;
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std::vector<RTLIL::SigSpec> connections_to_add_signal;
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dict<RTLIL::IdString, RTLIL::Module*> interfaces_to_add_to_submodule;
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dict<RTLIL::IdString, RTLIL::IdString> modports_used_in_submodule;
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// Reset the per-cell state
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void start_cell();
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// Set has_interfaces_not_found if there are pending interfaces that
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// haven't been found yet (and might be found in the future). Print a
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// warning if we've already gone over all the cells in the module.
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void on_missing_interface(RTLIL::IdString interface_name);
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// Handle an interface connection from the module
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void on_interface(RTLIL::Module &submodule,
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RTLIL::IdString conn_name,
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const RTLIL::SigSpec &conn_signals);
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// Handle a single connection from the module, making a note to expand
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// it if it's an interface connection.
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void on_connection(RTLIL::Module &submodule,
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RTLIL::IdString conn_name,
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const RTLIL::SigSpec &conn_signals);
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// Iterate over the connections in a cell, tracking any interface
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// connections
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void visit_connections(const RTLIL::Cell &cell,
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RTLIL::Module &submodule);
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// Add/remove connections to the cell as necessary, replacing any SV
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// interface port connection with the individual signal connections.
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void rewrite_interface_connections(RTLIL::Cell &cell) const;
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};
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};
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YOSYS_NAMESPACE_END
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#endif /* HIERARCHY_INTERFACES_H */
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