mirror of https://github.com/YosysHQ/yosys.git
85 lines
2.7 KiB
C++
85 lines
2.7 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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* Copyright (C) 2018 Ruben Undheim <ruben.undheim@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys_common.h"
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#include "passes/hierarchy/util/misc.h"
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#include "passes/hierarchy/util/clean.h"
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YOSYS_NAMESPACE_BEGIN
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namespace Hierarchy {
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void clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib)
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{
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std::set<RTLIL::Module*, IdString::compare_ptr_by_name<Module>> used;
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mark_used(design, used, top, 0);
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std::vector<RTLIL::Module*> del_modules;
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for (auto mod : design->modules())
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if (used.count(mod) == 0)
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del_modules.push_back(mod);
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else {
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// Now all interface ports must have been exploded, and it is hence
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// safe to delete all of the remaining dummy interface ports:
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pool<RTLIL::Wire*> del_wires;
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for(auto wire : mod->wires()) {
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if ((wire->port_input || wire->port_output) && wire->get_bool_attribute(ID::is_interface)) {
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del_wires.insert(wire);
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}
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}
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if (del_wires.size() > 0) {
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mod->remove(del_wires);
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mod->fixup_ports();
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}
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}
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int del_counter = 0;
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for (auto mod : del_modules) {
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if (!purge_lib && mod->get_blackbox_attribute())
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continue;
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log("Removing unused module `%s'.\n", mod->name);
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design->remove(mod);
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del_counter++;
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}
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log("Removed %d unused modules.\n", del_counter);
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}
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void mark_used(RTLIL::Design *design, std::set<RTLIL::Module*, IdString::compare_ptr_by_name<Module>> &used, RTLIL::Module *mod, int indent)
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{
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if (used.count(mod) > 0)
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return;
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if (indent == 0)
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log("Top module: %s\n", mod->name);
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else if (!mod->get_blackbox_attribute())
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log("Used module: %*s%s\n", indent, "", mod->name);
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used.insert(mod);
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for (auto cell : mod->cells()) {
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std::string celltype = cell->type.str();
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if (auto array_type = try_make_array(celltype))
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celltype = array_type->name;
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if (design->module(celltype))
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mark_used(design, used, design->module(celltype), indent+4);
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}
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}
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};
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YOSYS_NAMESPACE_END |