mirror of https://github.com/YosysHQ/yosys.git
13 lines
348 B
Python
13 lines
348 B
Python
#!/usr/bin/env python3
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import sys
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sys.path.append("..")
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import gen_tests_makefile
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gen_tests_makefile.generate_autotest("*.v", "",
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"""if grep -Eq 'expect-(wr-ports|rd-ports|rd-clk)' $@; then \\
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$(YOSYS) -f verilog -qp "proc; opt; memory -nomap; dump -outfile $(@:.v=).dmp t:\\$$mem_v2" $@; \\
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python3 validate.py $@ $(@:.v=).dmp; \\
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fi""")
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