Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-30 09:58:22 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
959a00a46ff65ec0cf82b6803cf7dd01f2ec4d39
yosys/techlibs/gowin
T
History
Eddie Hung 956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
..
.gitignore
gowin: Add missing .gitignore entries
2019-11-22 14:40:36 +01:00
arith_map.v
use ADDSUB ALU mode to remove inverters
2019-10-21 12:00:27 +02:00
brams_init3.vh
GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow
2019-04-12 23:40:02 -05:00
brams_init.py
support bram initialisation
2019-09-05 17:25:51 +02:00
brams_map.v
add 32-bit BRAM and byte-enables
2019-10-28 10:33:27 +01:00
brams.txt
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
2020-01-01 12:30:00 +00:00
cells_map.v
attempt to fix formatting
2019-11-25 14:50:34 +01:00
cells_sim.v
add IOBUF
2019-10-28 15:33:05 +01:00
determine_init.cc
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
lutrams_map.v
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
2020-01-01 12:30:00 +00:00
lutrams.txt
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
2020-01-01 12:30:00 +00:00
Makefile.inc
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
2020-01-01 12:30:00 +00:00
synth_gowin.cc
Removing cells_sim.v from bram techmap pass
2020-02-06 14:38:29 -06:00
Powered by Gitea Version: 1.27.2 Page: 481ms Template: 2ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API