mirror of https://github.com/YosysHQ/yosys.git
101 lines
1.7 KiB
Plaintext
101 lines
1.7 KiB
Plaintext
# Rewrite (2^k-1)-x into ~x when x is known to be smaller than 2^k
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read_verilog -icells <<EOT
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module test(input [3:0] b, output [3:0] y);
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$sub #(
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.A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(4),
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.A_SIGNED(0), .B_SIGNED(0),
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) sub (
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.A(4'hf), .B(b), .Y(y),
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);
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endmodule
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EOT
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$not
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select -assert-none t:$sub
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select -assert-none t:$not t:* %D
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design -reset
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read_verilog -icells <<EOT
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module test(input [1:0] b, output [3:0] y);
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$sub #(
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.A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(4),
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.A_SIGNED(0), .B_SIGNED(0),
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) sub (
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.A(4'd3), .B(b), .Y(y),
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);
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endmodule
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EOT
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$not
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select -assert-none t:$sub
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design -reset
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read_verilog -icells <<EOT
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module test(input [3:0] b, output [3:0] y);
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$sub #(
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.A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(4),
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.A_SIGNED(0), .B_SIGNED(0),
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) sub (
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.A(4'b1011), .B(b), .Y(y),
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);
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endmodule
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EOT
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-none t:$not
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design -reset
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read_verilog -icells <<EOT
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module test(input [3:0] b, output [3:0] y);
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$sub #(
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.A_WIDTH(2), .B_WIDTH(4), .Y_WIDTH(4),
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.A_SIGNED(0), .B_SIGNED(0),
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) sub (
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.A(2'b11), .B(b), .Y(y),
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);
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endmodule
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EOT
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-none t:$not
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design -reset
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read_verilog <<EOT
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module test(input [1:0] sel, input [0:3] data, output out);
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assign out = data[sel];
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endmodule
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EOT
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equiv_opt -assert opt -full
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design -load postopt
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select -assert-none t:$sub t:$add t:$alu
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design -reset
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read_verilog <<EOT
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module test(input sel, input [0:1] data, output out);
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assign out = data[sel];
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endmodule
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EOT
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equiv_opt -assert opt -full
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design -load postopt
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select -assert-none t:$sub t:$add t:$alu
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