mirror of https://github.com/YosysHQ/yosys.git
030d639201
Processes can contain `MemWriteAction` entries which are invisible to most passes operating on memories but which will be lowered to write ports later on by `proc_memwr`. For that reason we can get corrupted RTLIL if we sequence the memory passes before `proc`. Address that by making the affected memory passes ignore modules with processes. |
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| .. | ||
| Makefile.inc | ||
| memlib.cc | ||
| memlib.h | ||
| memlib.md | ||
| memory.cc | ||
| memory_bmux2rom.cc | ||
| memory_bram.cc | ||
| memory_collect.cc | ||
| memory_dff.cc | ||
| memory_libmap.cc | ||
| memory_map.cc | ||
| memory_memx.cc | ||
| memory_narrow.cc | ||
| memory_nordff.cc | ||
| memory_share.cc | ||
| memory_unpack.cc | ||