yosys/techlibs at 9509444ef2a55dcd75a6f5e1d96337f442238cee - yosys - Gitea: Git with a cup of tea

luke/yosys

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Xark 9509444ef2 Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH

2020-06-14 00:45:22 -07:00

..

Add force_downto and force_upto wire attributes.

2020-05-19 01:42:40 +02:00

Add force_downto and force_upto wire attributes.

2020-05-19 01:42:40 +02:00

Do not optimize away FFs in "prep" and Verific fron-end

2020-06-09 15:54:14 +02:00

Add force_downto and force_upto wire attributes.

2020-05-19 01:42:40 +02:00

Update doc that "-retime" calls abc with "-dff -D 1"

2019-12-30 13:28:29 -08:00

ecp5: cleanup unused +/ecp5/abc9_model.v

2020-05-23 08:17:40 -07:00

Add force_downto and force_upto wire attributes.

2020-05-19 01:42:40 +02:00

Add force_downto and force_upto wire attributes.

2020-05-19 01:42:40 +02:00

Add force_downto and force_upto wire attributes.

2020-05-19 01:42:40 +02:00

Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH

2020-06-14 00:45:22 -07:00

Add force_downto and force_upto wire attributes.

2020-05-19 01:42:40 +02:00

intel_alm: fix DFFE matching

2020-06-11 19:55:51 +02:00

Add force_downto and force_upto wire attributes.

2020-05-19 01:42:40 +02:00

xilinx: tidy up cells_sim.v a little

2020-05-25 09:48:11 -07:00

.gitignore

added .gitignore files

2013-01-05 11:19:11 +01:00