yosys/techlibs at 93f32b5dec8fdb116971ca0ddb17cdc993e7036c - yosys - Gitea: Git with a cup of tea

luke/yosys

mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-07 12:21:16 +02:00

Files

T

History

Clifford Wolf 0e7901e45c Merge pull request #941 from Wren6991/sim_lib_io_clke

ice40 cells_sim.v: update clock enable behaviour based on hardware experiments

2019-04-22 09:11:13 +02:00

..

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

Merge pull request #772 from whitequark/synth_lut

2019-01-02 15:44:57 +01:00

Unify usage of noflatten among architectures

2019-01-04 11:37:25 +01:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master

2019-04-22 09:09:27 +02:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware experiments

2019-04-21 21:40:11 +01:00

Fixing issues in CycloneV cell sim

2019-04-11 19:59:03 -05:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

Re-added clean after techmap in synth_xilinx

2019-04-22 09:03:11 +02:00

.gitignore

added .gitignore files

2013-01-05 11:19:11 +01:00