mirror of https://github.com/YosysHQ/yosys.git
93d19dc2fb
Don't pad logical operands to one bit. Use operand width and signedness in $reduce_bool. Shift amounts are unsigned and shouldn't be padded. Group "is invalid" with the wire declaration, not its use (otherwise it is incorrectly wired to 0). |
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| .gitignore | ||
| Makefile.inc | ||
| firrtl.cc | ||
| test.sh | ||
| test.v | ||