Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-29 09:30:28 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
92d70cafec026fb25bf45b020c138e5244bb8cdc
yosys/techlibs
T
History
Eddie Hung f68d723cdc Refactor +/cmp2lcu.v into recursive techmap
2020-04-03 14:28:22 -07:00
..
achronix
Remove executable flag from files
2020-02-15 10:36:44 +01:00
anlogic
synth_*: call 'opt -fast' after 'techmap'
2020-02-05 18:39:01 -08:00
common
Refactor +/cmp2lcu.v into recursive techmap
2020-04-03 14:28:22 -07:00
coolrunner2
coolrunner2: Attempt to give wires/cells more meaningful names
2020-03-02 01:40:57 -08:00
easic
Update doc that "-retime" calls abc with "-dff -D 1"
2019-12-30 13:28:29 -08:00
ecp5
Merge pull request #1716 from zeldin/ecp5_fix
2020-03-09 11:04:08 +01:00
efinix
synth_*: call 'opt -fast' after 'techmap'
2020-02-05 18:39:01 -08:00
gowin
Removing cells_sim.v from bram techmap pass
2020-02-06 14:38:29 -06:00
greenpak4
synth_*: call 'opt -fast' after 'techmap'
2020-02-05 18:39:01 -08:00
ice40
Fix indentation in techlibs/ice40/synth_ice40.cc.
2020-04-01 16:29:56 +00:00
intel
Add log_experimental() and experimental() API and "yosys -x"
2020-01-27 18:27:47 +01:00
sf2
synth_*: call 'opt -fast' after 'techmap'
2020-02-05 18:39:01 -08:00
xilinx
xilinx: Mark IOBUFDS.IOB as external pad
2020-03-20 14:37:38 +01:00
.gitignore
…
Powered by Gitea Version: 1.27.2 Page: 1632ms Template: 147ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API