Clifford Wolf 92cf7ae2f7 Added check: only one module for "show" unless format is "ps"

2013-03-27 18:31:42 +01:00

..

bitpattern.h

initial import

2013-01-05 11:13:26 +01:00

calc.cc

Moved stand-alone libs to libs/ directory and added libs/subcircuit

2013-02-27 09:32:19 +01:00

celltypes.h

Added additional functionality and cleanups in sigtools.h and celltypes.h

2013-03-15 10:22:23 +01:00

consteval.h

initial import

2013-01-05 11:13:26 +01:00

driver.cc

Added -S option for simple synthesis to gate logic

2013-03-21 09:52:21 +01:00

log.cc

initial import

2013-01-05 11:13:26 +01:00

log.h

initial import

2013-01-05 11:13:26 +01:00

register.cc

Added help -write-tex-command-reference-manual option

2013-03-21 11:33:56 +01:00

register.h

Implemented general handler for selection arguments

2013-03-03 10:05:37 +01:00

rtlil.cc

Create nice errors when calling RTLIL::Module::derive() of base class

2013-03-26 19:27:49 +01:00

rtlil.h

Added design->select() api and use it in extract pass

2013-03-03 20:53:24 +01:00

select.cc

fixed typos

2013-03-18 07:28:31 +01:00

show.cc

Added check: only one module for "show" unless format is "ps"

2013-03-27 18:31:42 +01:00

sigtools.h

Added additional functionality and cleanups in sigtools.h and celltypes.h

2013-03-15 10:22:23 +01:00