Eddie Hung 430a7548bc One more merge conflict

2019-02-17 11:50:55 -08:00

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aiger

Support and differentiate between ASCII and binary AIG testing

2019-02-08 12:41:59 -08:00

asicworld

Append (instead of over-writing) EXTRA_FLAGS

2019-02-15 11:56:51 -08:00

bram

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errors

Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,

2018-10-25 02:37:56 +03:00

fsm

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hana

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lut

cmp2lut: new techmap pass.

2019-01-02 07:53:31 +00:00

memories

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opt

opt_expr: improve simplification of comparisons with large constants.

2019-01-02 15:45:28 +00:00

realmath

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sat

Allow $size and $bits in verilog mode, actually check test case

2017-09-29 11:56:43 +02:00

share

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simple

Merge https://github.com/YosysHQ/yosys into read_aiger

2019-02-17 11:44:01 -08:00

simple_defparam

Add tests for simple cases using defparam

2019-02-06 14:15:17 -08:00

smv

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sva

Squelch a little more trailing whitespace

2018-12-29 12:46:54 +01:00

svinterfaces

Add missing .gitignore

2018-12-06 07:29:37 +01:00

techmap

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tools

One more merge conflict

2019-02-17 11:50:55 -08:00

unit

Build hotfix in tests/unit/Makefile

2016-12-11 10:58:49 +01:00

various

Modified errors into warnings

2018-06-05 18:03:22 +03:00

vloghtb

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