Clifford Wolf 91704a7853 Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys ...

(see https://github.com/cliffordwolf/yosys/pull/28)

2014-03-11 14:24:24 +01:00

..

bitpattern.h

initial import

2013-01-05 11:13:26 +01:00

calc.cc

Strictly zero-extend unsigned A-inputs of shift operations

2014-03-06 11:53:37 +01:00

celltypes.h

Fixed const folding of $bu0 cells

2014-02-27 04:09:32 +01:00

consteval.h

Fixed SAT and ConstEval undef handling for $pmux and $safe_pmux

2014-01-03 17:30:50 +01:00

driver.cc

Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys

2014-03-11 14:24:24 +01:00

log.cc

Added -v<level> option and some minor driver cleanups

2013-11-17 13:26:31 +01:00

log.h

Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys

2014-03-11 14:24:24 +01:00

register.cc

Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys

2014-03-11 14:24:24 +01:00

register.h

Added "design -push" and "design -pop"

2014-02-20 23:28:59 +01:00

rtlil.cc

Fixed a typo in RTLIL::Module::addReduce...

2014-03-10 12:07:26 +01:00

rtlil.h

Added RTLIL::Module::add... helper methods

2014-03-10 03:02:27 +01:00

satgen.h

Fixed use of frozen literals in SatGen

2014-03-06 13:08:44 +01:00

sigtools.h

Some fixes to improve determinism

2013-08-09 12:42:32 +02:00