Clifford Wolf 40d9542647 Implemented $_DFFSR_ expression generator in verilog backend

2013-11-21 21:52:30 +01:00

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autotest

Added support for complex set-reset flip-flops in proc_dff

2013-10-24 16:54:05 +02:00

blif

Write yosys version to output files

2013-11-03 21:41:39 +01:00

edif

Improved comments on topological sort in edif backend

2013-11-04 08:34:15 +01:00

ilang

Major improvements in mem2reg and added "init" sync rules

2013-11-21 13:49:00 +01:00

intersynth

Ignore explicit unconnected ports in intersynth backend

2013-11-03 09:00:51 +01:00

spice

Silenced a gcc warning in spice backend

2013-11-09 12:01:50 +01:00

verilog

Implemented $_DFFSR_ expression generator in verilog backend

2013-11-21 21:52:30 +01:00