yosys/techlibs at 8e53d2e0bf3584709cd320447ad5a89a80dcfd94 - yosys - Gitea: Git with a cup of tea

luke/yosys

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Clifford Wolf e09e49ca54 Merge pull request #766 from Icenowy/anlogic-latches

anlogic: add latch cells

2018-12-31 15:52:01 +01:00

..

Consistent use of 'override' for virtual methods in derived classes.

2018-07-20 23:51:06 -07:00

anlogic: add latch cells

2018-12-25 22:47:46 +08:00

gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.

2018-12-05 17:13:27 +00:00

Consistent use of 'override' for virtual methods in derived classes.

2018-07-20 23:51:06 -07:00

Consistent use of 'override' for virtual methods in derived classes.

2018-07-20 23:51:06 -07:00

Fix 7 instances of add_share_file to add_gen_share_file

2018-12-29 12:53:12 +01:00

Changes in GoWin synth commands and ALU primitive support

2018-12-03 20:08:35 -06:00

Consistent use of 'override' for virtual methods in derived classes.

2018-07-20 23:51:06 -07:00

Rename "fine:" label to "map:" in "synth_ice40"

2018-12-16 16:36:19 +01:00

Changes in GoWin synth commands and ALU primitive support

2018-12-03 20:08:35 -06:00

Fix sf2 LUT interface

2018-10-31 15:36:53 +01:00

Add support for Xilinx PS7 block

2018-11-10 12:45:07 -08:00

.gitignore

added .gitignore files

2013-01-05 11:19:11 +01:00