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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-06 20:12:09 +02:00
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8d60754aefbded7b5742ceae2b34fb6b4dcda93d
yosys/passes/opt
T
History
Clifford Wolf 8d60754aef Do not introduce new logic loops in "share"
2014-09-21 13:52:39 +02:00
..
Makefile.inc
Moved "share" and "wreduce" to passes/opt/
2014-09-01 11:45:26 +02:00
opt_clean.cc
Corrected spelling mistakes found by lintian
2014-09-06 08:47:06 +02:00
opt_const.cc
Fixed "opt_const -fine" for $pos cells
2014-09-04 08:55:58 +02:00
opt_muxtree.cc
Added design->scratchpad
2014-08-30 19:37:12 +02:00
opt_reduce.cc
Added design->scratchpad
2014-08-30 19:37:12 +02:00
opt_rmdff.cc
Added design->scratchpad
2014-08-30 19:37:12 +02:00
opt_share.cc
Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data
2014-09-01 11:36:02 +02:00
opt.cc
Added design->scratchpad
2014-08-30 19:37:12 +02:00
share.cc
Do not introduce new logic loops in "share"
2014-09-21 13:52:39 +02:00
wreduce.cc
Fixed wreduce $shiftx handling
2014-09-15 11:29:09 +02:00
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