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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-03 03:13:21 +02:00
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8d2b63bb8a1ed3e990aabaa4f0b93dccaea6df30
yosys/frontends
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History
Miodrag Milanovic 8d2b63bb8a Set VHDL assert condition initial state if fed by FF
2024-10-11 16:32:21 +02:00
..
aiger
read_aiger: Fix incorrect read of binary Aiger without outputs
2024-04-29 14:06:58 +01:00
aiger2
read_xaiger2: Add help
2024-10-07 14:19:49 +02:00
ast
Added cast to type support (#4284)
2024-09-29 17:03:01 -04:00
blif
Issue a warning instead of a syntax error for blif delay constraints
2024-01-23 16:25:16 +00:00
json
fix handling of escaped chars in json backend and frontend
2022-02-18 17:13:09 +01:00
liberty
read_liberty: Optionally import unit delay arcs
2024-09-18 16:17:03 +02:00
rpc
Fitting help messages to 80 character width
2022-08-24 10:40:57 +12:00
rtlil
Remove log
2024-08-21 14:28:42 +01:00
verific
Set VHDL assert condition initial state if fed by FF
2024-10-11 16:32:21 +02:00
verilog
Added cast to type support (#4284)
2024-09-29 17:03:01 -04:00
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