mirror of https://github.com/YosysHQ/yosys.git
53 lines
1.2 KiB
Plaintext
53 lines
1.2 KiB
Plaintext
pattern negmux
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//
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// Authored by Abhinav Tondapu of Silimate, Inc. under ISC license.
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//
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// Distribute negation over mux
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//
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// -(s ? a : b) ===> s ? (-a) : (-b)
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//
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state <SigSpec> neg_a neg_y mux_a mux_b mux_s
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state <bool> a_signed
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match neg
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select neg->type == $neg
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set neg_a port(neg, \A)
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set neg_y port(neg, \Y)
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set a_signed neg->getParam(\A_SIGNED).as_bool()
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endmatch
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match mux
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select mux->type == $mux
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index <SigSpec> port(mux, \Y) === neg_a
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select nusers(port(mux, \Y)) == 2
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set mux_a port(mux, \A)
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set mux_b port(mux, \B)
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set mux_s port(mux, \S)
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endmatch
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code neg_a neg_y mux_a mux_b mux_s a_signed
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{
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int width = GetSize(neg_y);
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SigSpec neg_mux_a = module->addWire(NEW_ID, width);
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Cell *neg_a_cell = module->addNeg(NEW_ID, mux_a, neg_mux_a, a_signed);
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SigSpec neg_mux_b = module->addWire(NEW_ID, width);
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Cell *neg_b_cell = module->addNeg(NEW_ID, mux_b, neg_mux_b, a_signed);
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Cell *new_mux = module->addMux(NEW_ID, neg_mux_a, neg_mux_b, mux_s, neg_y);
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log("negmux pattern in %s: neg=%s, mux=%s\n",
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log_id(module), log_id(neg), log_id(mux));
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neg_a_cell->fixup_parameters();
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neg_b_cell->fixup_parameters();
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new_mux->fixup_parameters();
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autoremove(neg);
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autoremove(mux);
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did_something = true;
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}
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accept;
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endcode
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