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20 lines
305 B
Plaintext
20 lines
305 B
Plaintext
read_verilog <<EOT
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(* blackbox *)
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module pad(inout B, output O);
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endmodule
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module top(input i, output o);
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wire a, b;
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assign a = i;
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assign b = i;
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pad p (.B(a), .O(o));
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endmodule
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EOT
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hierarchy -top top
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bufnorm -update
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bufnorm -reset
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clean
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check -assert
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select -assert-count 1 t:pad %x:+[B] w:i %i
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