Clifford Wolf 3650fd7fbe More fixes in ternary op sign handling

2013-07-12 13:13:04 +02:00

..

asicworld

Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.v

2013-05-24 15:15:59 +02:00

hana

added more .gitignore files (make test)

2013-01-05 11:35:52 +01:00

i2c_bench

initial import

2013-01-05 11:13:26 +01:00

k68_vltor

Now only use value from "initial" when no matching "always" block is found

2013-03-31 11:51:12 +02:00

no-icarus

initial import

2013-01-05 11:13:26 +01:00

simple

More fixes in ternary op sign handling

2013-07-12 13:13:04 +02:00

tools

Major redesign of expr width/sign detecion (verilog/ast frontend)

2013-07-09 14:31:57 +02:00