yosys/techlibs/quicklogic at 8bcec792e2db3714c58f8f81dc3ca4dce543ece0 - yosys - Gitea: Git with a cup of tea

luke/yosys

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Emil J. Tywoniak cd9b1191f2 signorm: disable in passes that use swap_names

2026-07-17 23:32:34 +02:00

..

synth_quicklogic: rearrange files to prepare for adding more architectures

2023-12-04 15:52:02 +01:00

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

CMakeLists.txt

Migrate build system to CMake

2026-06-03 08:58:10 +00:00

ql_bram_merge.cc

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

ql_bram_types.cc

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

ql_dsp_io_regs.cc

Refactored uses of log_id()

2026-05-08 20:59:24 -07:00

ql_dsp_macc.cc

Fixing couple more conversion errors

2026-05-14 15:58:58 +02:00

ql_dsp_macc.pmg

ql_dsp_macc: Tune DSP inference code

2023-12-04 15:52:02 +01:00

ql_dsp_simd.cc

Refactored uses of log_id()

2026-05-08 20:59:24 -07:00

ql_ioff.cc

signorm: disable in passes that use swap_names

2026-07-17 23:32:34 +02:00

synth_quicklogic.cc

Merge branch 'main' into nella/latch-toggle

2026-07-08 11:41:08 +02:00