Clifford Wolf 1f1deda888 Added non-std verilog assume() statement

2015-02-26 18:47:39 +01:00

..

abc

Fixed typos found by lintian

2015-02-01 21:49:55 +01:00

cmds

Fixed "check -assert"

2015-02-22 16:29:44 +01:00

equiv

Replaced ezDefaultSAT with ezSatPtr

2015-02-21 12:15:41 +01:00

fsm

Added onehot attribute

2015-02-04 18:52:54 +01:00

hierarchy

Cosmetic fixes in "hierarchy" for blackbox modules

2015-02-15 12:57:41 +01:00

memory

Replaced ezDefaultSAT with ezSatPtr

2015-02-21 12:15:41 +01:00

opt

Added non-std verilog assume() statement

2015-02-26 18:47:39 +01:00

proc

Fixed compilation problems with gcc 4.6.3; use enum instead of const ints.

2015-02-24 11:01:00 +01:00

sat

Added non-std verilog assume() statement

2015-02-26 18:47:39 +01:00

techmap

Merge branch 'master' of github.com:cliffordwolf/yosys

2015-02-25 23:01:54 +01:00

tests

Replaced ezDefaultSAT with ezSatPtr

2015-02-21 12:15:41 +01:00