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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-08 12:44:23 +02:00
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8af7ced5cd452bd0ef1e6bc17206e9360a893e49
yosys/backends
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Clifford Wolf 8af7ced5cd Merge pull request #1163 from whitequark/more-case-attrs
More support for case rule attributes
2019-07-09 18:48:47 +01:00
..
aiger
Fix gcc invalidation behaviour for write_aiger
2019-06-20 21:56:47 -07:00
blif
Fix handling of offset and upto module ports in write_blif, fixes #1040
2019-05-25 17:45:14 +02:00
btor
Improve BTOR2 handling of undriven wires
2019-06-26 17:42:00 +02:00
edif
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
firrtl
Fix static shift operands, neg result type, minor formatting
2019-05-21 13:04:56 -07:00
ilang
Merge pull request #1162 from whitequark/rtlil-case-attrs
2019-07-09 18:48:38 +01:00
intersynth
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
json
Fix json formatting
2019-06-21 20:01:40 +02:00
protobuf
Support filename rewrite in backends
2019-06-18 14:39:52 -07:00
simplec
Fix typographical and grammatical errors and inconsistencies.
2019-01-02 13:12:17 +00:00
smt2
Escape scope names starting with dollar sign in smtio.py
2019-06-26 10:58:39 +02:00
smv
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
spice
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
table
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
verilog
Merge pull request #1163 from whitequark/more-case-attrs
2019-07-09 18:48:47 +01:00
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