mirror of https://github.com/YosysHQ/yosys.git
23 lines
446 B
Python
23 lines
446 B
Python
from pyosys import libyosys as ys
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from pathlib import Path
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__file_dir__ = Path(__file__).absolute().parent
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d = ys.Design()
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class Monitor(ys.Monitor):
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def __init__(self):
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super().__init__()
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self.mods = []
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def notify_module_add(self, mod):
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self.mods.append(mod.name.str())
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m = Monitor()
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d.monitors.add(m)
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ys.run_pass(f"read_verilog {__file_dir__ / 'spm.cut.v.gz'}", d)
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ys.run_pass("hierarchy -top spm", d)
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assert m.mods == ["\\spm"]
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