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yosys/backends
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whitequark 3c643c57df write_verilog: add -extmem option, to write split memory init files. 
Some toolchains (in particular Quartus) are pathologically slow if
a large amount of assignments in `initial` blocks are used.
2019-11-18 01:27:21 +00:00
..
aiger
Fix write_aiger bug added in 524af21
2019-11-04 14:25:13 +01:00
blif
RTLIL::S{0,1} -> State::S{0,1}
2019-08-07 11:12:38 -07:00
btor
Use cell name for btor bad state props when it is a public name
2019-11-14 11:57:38 +01:00
edif
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firrtl
Merge pull request #1258 from YosysHQ/eddie/cleanup
2019-08-10 09:52:14 +02:00
ilang
RTLIL::S{0,1} -> State::S{0,1}
2019-08-07 11:12:38 -07:00
intersynth
substr() -> compare()
2019-08-07 12:20:08 -07:00
json
Implement improved JSON attr/param encoding
2019-08-01 12:34:52 +02:00
protobuf
Add aiger and protobuf backends binary support
2019-09-28 09:51:48 +02:00
simplec
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
2019-08-06 04:47:55 +02:00
smt2
Bugfix in smtio vcd handling of $-identifiers
2019-10-23 00:04:34 +02:00
smv
substr() -> compare()
2019-08-07 12:20:08 -07:00
spice
…
table
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verilog
write_verilog: add -extmem option, to write split memory init files.
2019-11-18 01:27:21 +00:00