Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-06 20:12:09 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
840c515ffc61cf6c8f5b79f9435c8fabbc8f7c75
yosys/passes
T
History
N. Engelhardt 0fc5812dcd Merge pull request #4541 from YosysHQ/krys/compiler-warnings
Resolve (some) compiler warnings
2024-08-26 15:04:16 +02:00
..
cmds
Improve libparse encapsulation
2024-08-13 18:47:36 +02:00
equiv
equiv_simple: Take FFs into account for driver map
2024-02-21 12:05:52 +01:00
fsm
add option to fsm_detect to ignore self-resetting
2023-01-30 16:12:53 +01:00
hierarchy
cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter
2024-07-29 10:26:02 +02:00
memory
memory_map: Explain -iattr better
2024-03-06 15:15:37 +01:00
opt
Merge pull request #4176 from povik/opt_expr-performance
2024-07-15 16:10:25 +02:00
pmgen
Merge pull request #4452 from phsauter/shiftadd-underflow-fix
2024-08-19 15:45:46 +02:00
proc
proc_rom: Set src on the emitted memory
2024-07-25 23:14:27 +01:00
sat
Set ranges on exported wires in VCD and FST
2024-08-02 15:23:00 +02:00
techmap
Address warnings
2024-08-16 04:30:31 +12:00
tests
cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter
2024-07-29 10:26:02 +02:00
Powered by Gitea Version: 1.27.2 Page: 2927ms Template: 138ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API