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67 lines
1.4 KiB
Plaintext
67 lines
1.4 KiB
Plaintext
read_rtlil <<EOF
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attribute \top 1
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module \top
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wire input 1 \clk
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wire inout 2 \port_b_0__io__io
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wire inout 3 \port_b_1__io__io
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wire width 8 input 4 \payload
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wire width 4 \o
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wire width 4 $5
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wire width 2 \o[0]
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wire width 2 \o[1]
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wire width 2 \o1
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cell \SB_IO \buf0
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parameter \IO_STANDARD "SB_LVCMOS"
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parameter \PULLUP 1
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parameter \PIN_TYPE 6'110001
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connect \OUTPUT_CLK \clk
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connect \D_OUT_0 \o [0]
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connect \D_OUT_1 \o1 [0]
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connect \OUTPUT_ENABLE 1'1
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connect \PACKAGE_PIN \port_b_0__io__io
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end
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cell \SB_IO \buf1
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parameter \IO_STANDARD "SB_LVCMOS"
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parameter \PULLUP 1
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parameter \PIN_TYPE 6'110001
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connect \OUTPUT_CLK \clk
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connect \D_OUT_0 \o [1]
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connect \D_OUT_1 \o1 [1]
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connect \OUTPUT_ENABLE 1'1
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connect \PACKAGE_PIN \port_b_1__io__io
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end
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cell \SB_DFF \dffsb0
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connect \C \clk
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connect \D \o [2]
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connect \Q \o1 [0]
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end
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cell \SB_DFF \dffsb1
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connect \C \clk
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connect \D \o [3]
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connect \Q \o1 [1]
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end
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cell $dff $dff
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parameter \WIDTH 4
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parameter \CLK_POLARITY 1
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connect \D $5
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connect \CLK \clk
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connect \Q \o
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end
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process $1
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assign $5 [1:0] { \payload [6] \payload [7] }
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assign $5 [3:2] { \payload [6] \payload [7] }
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end
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connect \o[0] \o [1:0]
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connect \o[1] \o [3:2]
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end
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EOF
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logger -expect prefix-warning "Feature 'write_xaiger2' is experimental." 1
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synth_ice40
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logger -expect-no-warnings
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