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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-03 19:19:48 +02:00
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8197169f8ddd7ef832e5f977bdcd2214d9c3bd1f
yosys/techlibs/common
T
History
Clifford Wolf 8197169f8d Added techmap rules for $sr, $dffsr and $dlatch
2013-10-18 12:29:21 +02:00
..
blackbox.sed
Moved common techlib files to techlibs/common
2013-09-15 11:52:57 +02:00
Makefile.inc
Moved common techlib files to techlibs/common
2013-09-15 11:52:57 +02:00
simlib.v
Added $sr, $dffsr and $dlatch cell types
2013-10-18 11:56:16 +02:00
stdcells_sim.v
Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_
2013-10-18 12:13:34 +02:00
stdcells.v
Added techmap rules for $sr, $dffsr and $dlatch
2013-10-18 12:29:21 +02:00
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