Udi Finkelstein 2b9c75f8e3 This PR should be the base for discussion, do not merge it yet! ... It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)		2018-03-11 23:09:34 +02:00
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.gitignore	Updated .gitignore file for ilang and verilog frontends	2014-10-15 01:14:38 +02:00
Makefile.inc	Adjust makefiles to work with out-of-tree builds	2015-08-12 15:04:44 +02:00
const2ast.cc	Fixed segfault on invalid verilog constant 1'b_	2015-09-22 08:13:09 +02:00
preproc.cc	Add support for "yosys -E"	2018-01-07 16:36:13 +01:00
verilog_frontend.cc	Bugfix in verilog_defaults argument parser	2017-12-24 17:21:37 +01:00
verilog_frontend.h	Remember global declarations and defines accross read_verilog calls	2016-11-15 12:42:43 +01:00
verilog_lexer.l	This PR should be the base for discussion, do not merge it yet!	2018-03-11 23:09:34 +02:00
verilog_parser.y	This PR should be the base for discussion, do not merge it yet!	2018-03-11 23:09:34 +02:00