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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 10:03:36 +02:00
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80c6a7eaf37da031b1b3e0c15997db6ea5c52cd5
yosys/passes
T
History
George Rennie 5c17f435a9 opt_merge: don't merge $barrier cells
2026-09-30 09:52:46 +02:00
..
cmds
Merge remote-tracking branch 'origin/main' into nella/latch-diagnostics-2
2026-09-22 16:49:41 +02:00
equiv
Docs: Minor tidying
2026-07-09 15:50:58 +12:00
fsm
opt_clean: move unused_bits analysis to kernel/unused_bits.h
2026-08-12 11:42:50 +02:00
hierarchy
Reject unknown internal cell types in check and hierarchy -check.
2026-09-14 13:50:09 +02:00
memory
Remove trailing whitespaces
2026-06-23 07:24:59 +02:00
opt
opt_merge: don't merge $barrier cells
2026-09-30 09:52:46 +02:00
pmgen
Migrate build system to CMake
2026-06-03 08:58:10 +00:00
proc
proc_dlatch: factor out traversal loop check
2026-09-29 17:36:00 +02:00
sat
Remove leftover use of log_id
2026-06-24 08:04:48 +02:00
techmap
abc_new: error handling when sketchy scripts are used
2026-09-30 12:19:21 +02:00
tests
End of file fix
2026-06-23 07:23:41 +02:00
CMakeLists.txt
Migrate build system to CMake
2026-06-03 08:58:10 +00:00
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