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809b94a67b0b666018b35536d4de327e99378a6f
yosys/techlibs/intel
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Ben Widawsky 809b94a67b intel_synth: Make family explicit and match
The help and code default to MAX10 for the family, however the couple of
if ladders defaulted to cycloneive. Fix this inconsistency and the next
patch will clean it up.

Signed-off-by: Ben Widawsky <[email protected]>
2019-07-18 17:06:03 +01:00
..
a10gx
Clean whitespace and permissions in techlibs/intel
2017-10-05 16:23:49 +02:00
common
Changes in GoWin synth commands and ALU primitive support
2018-12-03 20:08:35 -06:00
cyclone10
Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device
2018-03-31 22:48:47 -06:00
cycloneiv
Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device
2018-03-31 22:48:47 -06:00
cycloneive
Reduce amount of trailing whitespace in code base
2019-02-28 14:58:11 -08:00
cyclonev
Fixing issues in CycloneV cell sim
2019-04-11 19:59:03 -05:00
max10
Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device
2018-03-31 22:48:47 -06:00
Makefile.inc
Initial Cyclone 10 support
2017-11-08 22:45:21 -06:00
synth_intel.cc
intel_synth: Make family explicit and match
2019-07-18 17:06:03 +01:00
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