Clifford Wolf ba407da187 Added addBufGate module method

2016-02-02 11:26:07 +01:00

..

ast

genrtlil: avoid converting SigSpec to set<SigBit> when going through removeSignalFromCaseTree()

2016-01-31 09:20:16 -08:00

blif

Various improvements in BLIF front-end

2015-12-20 13:12:24 +01:00

ilang

Fixed oom bug in ilang parser

2015-11-29 20:30:32 +01:00

liberty

Fixed trailing whitespaces

2015-07-02 11:14:30 +02:00

verific

Added addBufGate module method

2016-02-02 11:26:07 +01:00

verilog

Fixed handling of parameters and localparams in functions

2015-11-11 10:54:35 +01:00

vhdl2verilog

Fixed trailing whitespaces

2015-07-02 11:14:30 +02:00