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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-07 04:19:56 +02:00
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7fecc3c199e6cfe4b474431d54027d699bc8d343
yosys/frontends
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Clifford Wolf 9a946c207f Add comment to VIPER #13453 work-around
Signed-off-by: Clifford Wolf <[email protected]>
2018-05-28 13:36:35 +02:00
..
ast
Replace -ignore_redef with -[no]overwrite
2018-05-03 15:25:59 +02:00
blif
Increase maximum LUT size in blifparse to 12 bits
2017-09-27 15:27:42 +02:00
ilang
Added avail params to ilang format, check module params in 'hierarchy -check'
2016-10-22 11:05:49 +02:00
json
Parse reals as string in JSON front-end
2017-09-26 14:37:03 +02:00
liberty
Also interpret '&' in liberty functions
2018-05-12 20:55:31 +02:00
verific
Add comment to VIPER #13453 work-around
2018-05-28 13:36:35 +02:00
verilog
Support SystemVerilog `` extension for macros
2018-05-17 00:09:56 -04:00
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