yosys/techlibs/quicklogic at 7fe32137bdf7c78bfccb8ba09e6fdfddfdf57a90 - yosys - Gitea: Git with a cup of tea

luke/yosys

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nella fff034d2f8 Add check before flatten in synth_*.

2026-05-05 14:06:58 +02:00

..

synth_quicklogic: rearrange files to prepare for adding more architectures

2023-12-04 15:52:02 +01:00

synth_quicklogic: rearrange files to prepare for adding more architectures

2023-12-04 15:52:02 +01:00

Drop timestamp in generate_bram_types_sim.py

2024-10-30 08:47:18 +01:00

.gitignore

add dsp inference

2023-12-04 15:52:02 +01:00

Makefile.inc

add ioff inference for qlf_k6n10f

2025-01-24 21:17:15 +01:00

ql_bram_merge.cc

Use fast path for 32-bit Const integer constructor in more places

2025-09-16 03:17:24 +00:00

ql_bram_types.cc

add dsp inference

2023-12-04 15:52:02 +01:00

ql_dsp_io_regs.cc

Fix Windows build by forcing initialization order, fixes #4068

2024-01-02 11:26:48 +01:00

ql_dsp_macc.cc

Fix out of tree build

2023-12-06 09:11:51 +01:00

ql_dsp_macc.pmg

ql_dsp_macc: Tune DSP inference code

2023-12-04 15:52:02 +01:00

ql_dsp_simd.cc

Update techlibs to avoid bits()

2025-09-16 03:17:23 +00:00

ql_ioff.cc

Remove .c_str() from parameters to log_debug()

2025-09-23 19:10:33 +12:00

synth_quicklogic.cc

Add check before flatten in synth_*.

2026-05-05 14:06:58 +02:00