Charlotte 4e94f62116 simlib: blackbox $print cell ...

It's possible to `generate` the appropriate always blocks per the
triggers, but unlikely to be worth parsing the RTLIL \FORMAT parameter.

2023-08-11 04:46:52 +02:00

..

.gitignore

Added first help messages for cell types

2015-10-14 16:27:42 +02:00

abc9_map.v

techmap: Add support for [] wildcards in techmap_celltype.

2020-08-02 22:46:48 +02:00

abc9_model.v

abc9: fix SCC issues (#2694)

2021-03-29 22:01:57 -07:00

abc9_unmap.v

abc9: fix SCC issues (#2694)

2021-03-29 22:01:57 -07:00

adff2dff.v

Fix syntax error in adff2dff.v

2021-02-24 01:07:34 +01:00

cellhelp.py

Progress on cell help messages

2015-10-17 02:35:19 +02:00

cells.lib

Added cells.lib

2015-01-16 15:50:42 +01:00

cmp2lcu.v

verilog: significant block scoping improvements

2021-01-31 09:42:09 -05:00

cmp2lut.v

verilog: significant block scoping improvements

2021-01-31 09:42:09 -05:00

dff2ff.v

Add force_downto and force_upto wire attributes.

2020-05-19 01:42:40 +02:00

gate2lut.v

Fix invalid verilog syntax

2020-03-14 14:33:44 +01:00

gen_fine_ffs.py

Add $aldff and $aldffe: flip-flops with async load.

2021-10-02 18:12:52 +02:00

Makefile.inc

Add smtmap.v describing the smt2 backend's behavior for undef bits

2022-10-20 15:48:18 +02:00

mul2dsp.v

Fix files with CRLF line endings

2021-06-09 12:16:33 +02:00

pmux2mux.v

Added techlibs/common/pmux2mux.v

2014-01-17 20:06:15 +01:00

prep.cc

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

simcells.v

Add $aldff and $aldffe: flip-flops with async load.

2021-10-02 18:12:52 +02:00

simlib.v

simlib: blackbox $print cell

2023-08-11 04:46:52 +02:00

smtmap.v

Add smtmap.v describing the smt2 backend's behavior for undef bits

2022-10-20 15:48:18 +02:00

synth.cc

Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}.

2022-06-02 23:16:12 +02:00

techmap.v

Add bitwise $bweqx and $bwmux cells

2022-11-30 18:24:35 +01:00