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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-08 12:44:23 +02:00
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7f791a4fb97ebc95346d5a0cf66c85628ae88f23
yosys/passes/proc
T
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Emil J. Tywoniak 7f791a4fb9 proc_dff: better error context
(cherry picked from commit 404ce980e4)
2026-07-20 15:01:30 +02:00
..
CMakeLists.txt
Migrate build system to CMake
2026-06-03 08:58:10 +00:00
proc_arst.cc
rtlil: add source tracking to CaseRule actions
2026-07-20 15:01:30 +02:00
proc_clean.cc
rtlil: replace SigSig actions with new type SyncAction
2026-07-20 15:01:30 +02:00
proc_dff.cc
proc_dff: better error context
2026-07-20 15:01:30 +02:00
proc_dlatch.cc
rtlil: replace SigSig actions with new type SyncAction
2026-07-20 15:01:30 +02:00
proc_init.cc
rtlil: replace SigSig actions with new type SyncAction
2026-07-20 15:01:30 +02:00
proc_memwr.cc
WIP
2026-07-20 12:27:17 +02:00
proc_mux.cc
proc_mux: include switch expression location in $eq src
2026-07-20 15:01:30 +02:00
proc_prune.cc
rtlil: replace SigSig actions with new type SyncAction
2026-07-20 15:01:30 +02:00
proc_rmdead.cc
WIP migration to twine
2026-07-20 12:27:18 +02:00
proc_rom.cc
rtlil: add source tracking to CaseRule actions
2026-07-20 15:01:30 +02:00
proc.cc
Add latch inference msg severity option.
2026-06-15 14:17:02 +02:00
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