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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-06 11:59:46 +02:00
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7f734ecc098a2a113ced835cefc9d4e1982f08d0
yosys/passes/fsm
T
History
Clifford Wolf 7f734ecc09 Added module->uniquify()
2014-08-16 23:50:36 +02:00
..
fsm_detect.cc
RIP $safe_pmux
2014-08-14 11:39:46 +02:00
fsm_expand.cc
More idstring sort_by_* helpers and fixed tpl ordering in techmap
2014-08-15 02:40:46 +02:00
fsm_export.cc
Fixed "fsm -export"
2014-08-08 14:56:03 +02:00
fsm_extract.cc
RIP $safe_pmux
2014-08-14 11:39:46 +02:00
fsm_info.cc
Refactoring: Renamed RTLIL::Design::modules to modules_
2014-07-27 11:18:30 +02:00
fsm_map.cc
Added module->uniquify()
2014-08-16 23:50:36 +02:00
fsm_opt.cc
Some improvements in fsm_opt and fsm_map for FSM with unreachable states
2014-08-09 14:49:51 +02:00
fsm_recode.cc
Some improvements in FSM mapping and recoding
2014-08-14 11:22:45 +02:00
fsm.cc
Fixed "fsm -export"
2014-08-08 14:56:03 +02:00
fsmdata.h
Renamed port access function on RTLIL::Cell, added param access functions
2014-07-31 16:38:54 +02:00
Makefile.inc
initial import
2013-01-05 11:13:26 +01:00
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