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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-06 11:59:46 +02:00
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7f734ecc098a2a113ced835cefc9d4e1982f08d0
yosys/frontends/verilog
T
History
Clifford Wolf 6d56172c0d Fixed line numbers when using here-doc macros
2014-08-14 22:26:30 +02:00
..
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
const2ast.cc
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
2014-07-31 13:19:47 +02:00
lexer.l
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
2014-07-31 13:19:47 +02:00
Makefile.inc
Added "make PRETTY=1"
2014-07-24 17:15:01 +02:00
parser.y
Also allow "module foobar(input foo, output bar, ...);" syntax
2014-08-07 16:41:27 +02:00
preproc.cc
Fixed line numbers when using here-doc macros
2014-08-14 22:26:30 +02:00
verilog_frontend.cc
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
2014-07-31 13:19:47 +02:00
verilog_frontend.h
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
2014-07-31 13:19:47 +02:00
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