yosys/passes/techmap at 7f3dc86ecd00a9ed5f5b7f09e02a6fe584259f79 - yosys - Gitea: Git with a cup of tea

luke/yosys

mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-01 02:27:34 +02:00

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History

Clifford Wolf 4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_

2014-07-27 01:51:45 +02:00

..

.gitignore

added .gitignore files

2013-01-05 11:19:11 +01:00

dfflibmap.cc

Refactoring: Renamed RTLIL::Module::cells to cells_

2014-07-27 01:51:45 +02:00

extract.cc

Refactoring: Renamed RTLIL::Module::cells to cells_

2014-07-27 01:51:45 +02:00

filterlib.cc

Moved dfflibmap from passes/dfflibmap to passes/techmap

2013-10-16 15:32:26 +02:00

hilomap.cc

Manual fixes for new cell connections API

2014-07-26 15:58:23 +02:00

iopadmap.cc

Refactoring: Renamed RTLIL::Module::wires to wires_

2014-07-27 01:49:51 +02:00

libparse.cc

Fixed dumping of timing() { .. } block in libparse

2014-03-09 15:16:07 +01:00

libparse.h

renamed LibertyParer to LibertyParser

2014-01-14 18:57:47 +01:00

Makefile.inc

Added "make SMALL=1"

2014-07-24 19:03:57 +02:00

simplemap.cc

Refactoring: Renamed RTLIL::Module::cells to cells_

2014-07-27 01:51:45 +02:00

techmap.cc

Refactoring: Renamed RTLIL::Module::cells to cells_

2014-07-27 01:51:45 +02:00