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7f3dc86ecd00a9ed5f5b7f09e02a6fe584259f79
yosys
/
passes
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proc
T
History
Clifford Wolf
4c4b602156
Refactoring: Renamed RTLIL::Module::cells to cells_
2014-07-27 01:51:45 +02:00
..
Makefile.inc
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
proc_arst.cc
Refactoring: Renamed RTLIL::Module::cells to cells_
2014-07-27 01:51:45 +02:00
proc_clean.cc
SigSpec refactoring: using the accessor functions everywhere
2014-07-22 20:39:37 +02:00
proc_dff.cc
Manual fixes for new cell connections API
2014-07-26 15:58:23 +02:00
proc_init.cc
Replaced more old SigChunk programming patterns
2014-07-24 23:10:58 +02:00
proc_mux.cc
Changed a lot of code to the new RTLIL::Wire constructors
2014-07-26 20:12:50 +02:00
proc_rmdead.cc
Added help messages to proc_* passes
2013-03-01 09:26:29 +01:00
proc.cc
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
